Fix wiring up of resets and clocks

Author: robtaylor

chipflow_lib/platforms/sim.py

@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
+import logging
 import os
 import sys
 from pathlib import Path
@@ -14,6 +15,7 @@
 
 
 __all__ = ["SimPlatform"]
+logger = logging.getLogger(__name__)
 
 
 class SimPlatform:
@@ -42,6 +44,7 @@ def build(self, e):
             if port.direction is io.Direction.Bidir:
                 ports.append((f"io${port_name}$oe", port.oe, PortDirection.Output))
 
+        print("elaborating design")
         output = rtlil.convert(e, name="sim_top", ports=ports, platform=self)
 
         top_rtlil = Path(self.build_dir) / "sim_soc.il"
@@ -73,19 +76,26 @@ def instantiate_ports(self, m: Module):
         for component, iface in pinlock.port_map.ports.items():
             for k, v in iface.items():
                 for name, port in v.items():
+                   logger.debug(f"Instantiating port {port.port_name}: {port}")
                    invert = port.invert if port.invert else False
                    self._ports[port.port_name] = io.SimulationPort(port.direction, port.width, invert=invert, name=f"{component}-{name}")
 
         for clock in pinlock.port_map.get_clocks():
-            setattr(m.domains, clock.port_name, ClockDomain(name=clock.port_name))
+            assert 'clock_domain_o' in clock.iomodel
+            domain = clock.iomodel['clock_domain_o']
+            logger.debug(f"Instantiating clock buffer for {clock.port_name}, domain {domain}")
+            setattr(m.domains, domain, ClockDomain(name=domain))
             clk_buffer = io.Buffer(clock.direction, self._ports[clock.port_name])
             setattr(m.submodules, "clk_buffer_" + clock.port_name, clk_buffer)
             m.d.comb += ClockSignal().eq(clk_buffer.i)  # type: ignore[reportAttributeAccessIssue]
 
         for reset in pinlock.port_map.get_resets():
+            assert 'clock_domain_o' in reset.iomodel
+            domain = reset.iomodel['clock_domain_o']
+            logger.debug(f"Instantiating reset synchronizer for {reset.port_name}, domain {domain}")
             rst_buffer = io.Buffer(reset.direction, self._ports[clock.port_name])
             setattr(m.submodules, reset.port_name, rst_buffer)
-            ffsync = FFSynchronizer(rst_buffer.i, ResetSignal(name=reset.port_name))  # type: ignore[reportAttributeAccessIssue]
+            ffsync = FFSynchronizer(rst_buffer.i, ResetSignal())  # type: ignore[reportAttributeAccessIssue]
             setattr(m.submodules, reset.port_name + "_sync", ffsync)
 
         self._pinlock = pinlock

chipflow_lib/platforms/utils.py

@@ -332,17 +332,16 @@ def width(self):
 
     @property
     def direction(self):
-        assert self.pins and 'direction' in self.iomodel
-        assert len(self.pins) == self.iomodel['direction']
+        assert 'direction' in self.iomodel
         return self.iomodel['direction']
 
     @property
-    def invert(self) -> Iterable[bool]:
-        assert self.pins and 'invert' in self.iomodel
-        print(type(self.iomodel['invert']))
-        assert type(self.iomodel['invert']) is tuple
-        assert len(self.pins) == len(self.iomodel['invert'])
-        return self.iomodel['invert']
+    def invert(self) -> Iterable[bool] | None:
+        if 'invert' in self.iomodel:
+            assert type(self.iomodel['invert']) is tuple
+            return self.iomodel['invert']
+        else:
+            return None
 
 
 def _group_consecutive_items(ordering: PinList, lst: PinList) -> OrderedDict[int, List[PinList]]:
@@ -623,7 +622,7 @@ def _allocate_bringup(self, config: 'Config') -> Component:
                           'sync-rst_n': Port(type='reset',
                                            pins=[self.bringup_pins.core_reset],
                                            port_name='sync-rst_n',
-                                           iomodel=IOModel(width=1, direction=io.Direction.Input, clock_domain_o="sync", 
+                                           iomodel=IOModel(width=1, direction=io.Direction.Input, clock_domain_o="sync",
                                                            invert=True)
                                       )
                        }

chipflow_lib/software/soft_gen.py

@@ -11,9 +11,11 @@ def __init__(self, *, rom_start, rom_size, ram_start, ram_size):
         self.defines = []
         self.periphs = []
         self.extra_init = []
+        print("initialed SoftwareGenerator")
 
     def generate(self, out_dir):
         Path(out_dir).mkdir(parents=True, exist_ok=True)
+        print(f"generating in {out_dir}")
         with open(Path(out_dir) / "start.S", "w") as f:
             f.write(self.start)
         with open(Path(out_dir) / "sections.lds", "w") as f:

chipflow_lib/steps/__init__.py

@@ -41,25 +41,27 @@ def build_cli_parser(self, parser):
 
     def run_cli(self, args):
         "Called when this step's is used from `chipflow` command"
+        self.build()
+
+    def build(self, *args):
+        "builds the design"
         ...
 
 def _wire_up_ports(m: Module, top, platform):
-    logger.debug("wiring up ports")
-    logger.debug("adding top:")
+    logger.debug("Wiring up ports")
+    logger.debug("-> Adding top components:")
     for n, t in top.items():
         logger.debug(f"    > {n}, {t}")
         setattr(m.submodules, n, t)
-
-    logger.debug("wiring up:")
+    print("Wiring up ports:")
     for component, iface in platform._pinlock.port_map.ports.items():
         if component.startswith('_'):
             logger.debug(f"Ignoring special component {component}")
             continue
 
         for iface_name, member, in iface.items():
             for name, port in member.items():
-                logger.debug(f"    > {component}, {iface_name}, {member}")
-
+                logger.debug(f"    > {component}, {iface_name}, {name}: {port}")
                 iface = getattr(top[component], iface_name)
                 wire = (iface if isinstance(iface.signature, IOSignature)
                         else getattr(iface, name))

chipflow_lib/steps/board.py

@@ -14,6 +14,6 @@ def build_cli_parser(self, parser):
     def run_cli(self, args):
         self.build()
 
-    def build(self):
+    def build(self, *args):
         "Build for the given platform"
-        self.platform.build()
+        self.platform.build(*args)

chipflow_lib/steps/sim.py

@@ -77,7 +77,8 @@ def __init__(self, config):
         self._platform = SimPlatform(config)
         self._config = config
 
-    def build(self):
+    def build(self, *args):
+        print("building sim")
         m = Module()
         self._platform.instantiate_ports(m)
 

chipflow_lib/steps/software.py

@@ -4,13 +4,15 @@
 from doit.doit_cmd import DoitMain
 
 from . import StepBase
+from ..platforms import SimPlatform
 
 class SoftwareStep(StepBase):
     """Base step to build the software."""
 
     doit_build_module = None
 
     def __init__(self, config):
+        self._platform = SimPlatform(config)
         pass
 
     def build_cli_parser(self, parser):
@@ -23,6 +25,7 @@ def doit_build(self):
         "Run the overridden doit_build_module"
         DoitMain(ModuleTaskLoader(self.doit_build_module)).run(["build_software"])
 
-    def build(self):
+    def build(self, *args):
         "Build the software for your design"
+        print("building software")
         self.doit_build()