wip

Author: robtaylor

chipflow_lib/platforms/_utils.py

@@ -180,8 +180,9 @@ def model_post_init(self, __context):
 
     @property
     def width(self):
-        assert self.pins and 'width' in self.iomodel
-        assert len(self.pins) == self.iomodel['width']
+        assert 'width' in self.iomodel
+        if self.pins:
+            assert len(self.pins) == self.iomodel['width']
         return self.iomodel['width']
 
     @property
@@ -206,6 +207,40 @@ def interface_power_domain(self) -> str | None:
             return None
 
 
+def create_ports(name: str, member: Dict[str, Any], port_name: str) -> Dict[str, Port]:
+    "Allocate pins based of Amaranth member metadata"
+    pin_map: Dict[str, Port] = {}
+
+    logger.debug(f"create_ports: name={name}")
+    logger.debug(f"member={pformat(member)}")
+
+    if member['type'] == 'interface' and 'annotations' in member \
+       and IO_ANNOTATION_SCHEMA in member['annotations']:
+        model:IOModel = member['annotations'][IO_ANNOTATION_SCHEMA]
+        logger.debug(f"matched IOSignature {model}")
+        pin_map[name] = Port(type='io', port_name=port_name, iomodel=model, pins=None)
+        logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
+        return pin_map
+    elif member['type'] == 'interface':
+        for k, v in member['members'].items():
+            port_name = '_'.join([name, k])
+            _map = create_ports(name=k, member=v, port_name=port_name)
+            pin_map |= _map
+            logger.debug(f"{pin_map},{_map}")
+        return pin_map
+    elif member['type'] == 'port':
+        logger.warning(f"Port '{name}' has no IOSignature, pin allocation likely to be wrong")
+        width = member['width']
+        model = IOModel(width=width, direction=io.Direction(member['dir']))
+        pin_map[name] = Port(type='io', port_name=port_name, iomodel=model, pins=None)
+        logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
+        return pin_map
+    else:
+        logging.debug(f"Shouldnt get here. member = {member}")
+        assert False
+
+
+
 Interface = Dict[str, Port]
 Component = Dict[str, Interface]
 AllocateFunc = Callable[[PinSet, int], PinList]
@@ -272,16 +307,10 @@ def populate(self, interfaces: dict, lockfile: Optional['LockFile'] = None):
                         )
                     self.add_ports(component, interface, old_ports)
                 else:
-                    print(f"i {interface}, v {v}")
-                    for name, member in v['members'].items():
-                        print(member)
-                        if member['type'] == 'interface' and 'annotations' in member \
-                        and IO_ANNOTATION_SCHEMA in member['annotations']:
-                            iomodel: IOModel = member['annotations'][IO_ANNOTATION_SCHEMA]
-                            port = Port(type='io', pins=None, port_name=name, iomodel=iomodel)
-                            self.add_port(component, interface, name, port)
-                        else
-
+                    print(f"Creating ports for component: {component}, interface: {interface}")
+                    if component not in self.ports:
+                        self.ports[component] = {}
+                    self.ports[component][interface] = create_ports(interface, v, interface)
 
     def allocate_power(self, config: 'Config'):
         "Allocate power domains to top level ports"