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Merge branch 'benesd_feat_thunderfjord' into 'devel'
Add support for fb2cdg1 (ThunderFjord) card See merge request ndk/ndk-fpga!235
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‎apps/minimal/build/fb2cdg1/Makefile‎

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# Makefile: Makefile for Silicom ThunderFjord fb2cdg1 card
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# Copyright (C) 2025 DynaNIC Semiconductors Ltd.
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# Author(s): David Beneš <benes@dyna-nic.com>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# Set path to top-level of NDK-FPGA repository
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COMBO_BASE = ../../../..
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CARD_BASE = $(COMBO_BASE)/cards/silicom/fb2cdg1
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APP_CONF = app_conf.tcl
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PCIE_CONF ?= 1xgen5x8x8
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export PCIE_CONF
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OUTPUT_NAME = fb2cdg1-minimal-pcie$(PCIE_CONF)
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.PHONY: all 400g2
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all: 400g2
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400g2: ETH_PORTS=2
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400g2: ETH_PORT_SPEED=400
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400g2: ETH_PORT_CHAN=1
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400g2: EHIP_PORT_TYPE=0
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400g2: OUTPUT_NAME:=$(OUTPUT_NAME)-400g2
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400g2: build
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include $(CARD_BASE)/src/card.mk

‎apps/minimal/build/fb2cdg1/Quartus.tcl‎

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# Quartus.tcl: Quartus tcl script to compile whole FPGA design
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# Copyright (C) 2022 CESNET z. s. p. o.
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# Author(s): Jakub Cabal <cabal@cesnet.cz>
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# Vladislav Valek <valekv@cesnet.cz>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# NOTE: The purpose of this file is described in the Parameterization section of
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# the NDK-CORE documentation.
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# ----- Setting basic synthesis options ---------------------------------------
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# NDK & user constants
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source $env(CARD_BASE)/src/Quartus.inc.tcl
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# Create only a Quartus project for further design flow driven from Quartus GUI
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# "0" ... full design flow in command line
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# "1" ... project composition only for further dedesign flow in GUI
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set SYNTH_FLAGS(PROJ_ONLY) "0"
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# Associative array which is propagated to APPLICATION_CORE, add other
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# parameters if necessary.
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set APP_ARCHGRP(APP_CORE_ENABLE) $APP_CORE_ENABLE
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# Convert associative array to list
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set APP_ARCHGRP_L [array get APP_ARCHGRP]
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# ----- Add application core to main component list ---------------------------
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lappend HIERARCHY(COMPONENTS) \
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[list "APPLICATION_CORE" "$OFM_PATH/apps/minimal/top" $APP_ARCHGRP_L]
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# Call main function which handle targets
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nb_main

‎apps/minimal/build/fb2cdg1/app_conf.tcl‎

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# app_conf.tcl: User parameters for Silicom ThunderFjord fb2cdg1 card
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# Copyright (C) 2025 DynaNIC Semiconductors Ltd.
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# Author(s): David Beneš <benes@dyna-nic.com>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# NOTE: Use the PCIE_CONF make parameter to select the PCIe configuration.
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# ------------------------------------------------------------------------------
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# DMA parameters:
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# ------------------------------------------------------------------------------
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if {$env(DMA_TYPE) == 4} {
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# DMA Calypte not meet timing on R-Tile FPGAs with more than 16 channels.
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set DMA_RX_CHANNELS 16
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set DMA_TX_CHANNELS 16
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} else {
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# 400G DMA Medusa requires at least 32 channels.
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set DMA_RX_CHANNELS 32
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set DMA_TX_CHANNELS 32
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}
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# In blocking mode, packets are dropped only when the RX DMA channel is off.
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# In non-blocking mode, packets are dropped whenever they cannot be sent.
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set DMA_RX_BLOCKING_MODE true
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# ------------------------------------------------------------------------------
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# Other parameters:
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# ------------------------------------------------------------------------------
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set PROJECT_NAME "NDK_MINIMAL"
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set PROJECT_VARIANT "$ETH_PORT_SPEED(0)G$ETH_PORTS"
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set PROJECT_VERSION [exec cat ../../../../VERSION]

‎cards/silicom/fb2cdg1/config/card_conf.tcl‎

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# card_conf.tcl: Default parameters for Silicom ThunderFjord fb2cdg1
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# Copyright (C) 2025 DynaNIC Semiconductors, Ltd.
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# Author(s): David Beneš <benes@dyna-nic.com>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# NOTE: For the detailed description of this file, visit the Parametrization section
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# in the documentation of the NDK-CORE repository.
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#
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# Mandatory project parameters
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set PROJECT_NAME ""
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# ------------------------------------------------------------------------------
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# ETH parameters:
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# ------------------------------------------------------------------------------
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# Number of Ethernet ports, must match number of items in list ETH_PORTS_SPEED !
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set ETH_PORTS 2
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# Speed for each one of the ETH_PORTS (allowed values: 400, 200, 100, 50, 40, 25, 10)
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# ETH_PORT_SPEED is an array where each index represents given ETH_PORT and
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# each index has associated a required port speed.
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# NOTE: at this moment, all ports must have same speed !
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set ETH_PORT_SPEED(0) $env(ETH_PORT_SPEED)
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set ETH_PORT_SPEED(1) $env(ETH_PORT_SPEED)
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# Number of channels for each one of the ETH_PORTS (allowed values: 1, 2, 4, 8)
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# ETH_PORT_CHAN is an array where each index represents given ETH_PORT and
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# each index has associated a required number of channels this port has.
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# NOTE: at this moment, all ports must have same number of channels !
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set ETH_PORT_CHAN(0) $env(ETH_PORT_CHAN)
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set ETH_PORT_CHAN(1) $env(ETH_PORT_CHAN)
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# Number of lanes for each one of the ETH_PORTS
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# Typical values: 4 (QSFP), 8 (QSFP-DD)
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set ETH_PORT_LANES(0) 8
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set ETH_PORT_LANES(1) 8
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# EHIP_PORT_TYPE is an array where each index represents given ETH_PORT and
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# each index has associated a required type of IP core, which this port has.
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# NOTE: at this moment, all ports must have same type of IP core !
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set EHIP_PORT_TYPE(0) $env(EHIP_PORT_TYPE)
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set EHIP_PORT_TYPE(1) $env(EHIP_PORT_TYPE)
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# ------------------------------------------------------------------------------
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# PCIe parameters (not all combinations work):
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# ------------------------------------------------------------------------------
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# Supported combinations for this card:
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# 1x PCIe Gen4 x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Calypte)
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# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: for DMA Medusa only)
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# 1x PCIe Gen5 x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Medusa only)
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# ------------------------------------------------------------------------------
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# Set default PCIe configuration
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set PCIE_CONF "1xGen5x8x8"
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if { [info exist env(PCIE_CONF)] } {
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set PCIE_CONF $env(PCIE_CONF)
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}
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# Parsing PCIE_CONF string to list of parameters
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set pcie_conf_list [ParsePcieConf $PCIE_CONF]
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# PCIe Generation (possible values: 4, 5):
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# 4 = PCIe Gen4 (Stratix 10 with P-Tile or Agilex)
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# 5 = PCIe Gen5 (Agilex with R-Tile)
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set PCIE_GEN [lindex $pcie_conf_list 1]
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# PCIe endpoints (possible values: 2, 4):
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# 2 = 2x PCIe x16 in two slot OR 2x PCIe x8 in one slot (bifurcation x8+x8)
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# 4 = 4x PCIe x8 in two slots (bifurcation x8+x8)
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set PCIE_ENDPOINTS [lindex $pcie_conf_list 0]
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# PCIe endpoint mode (possible values: 1):
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# 1 = 2x8 lanes (bifurcation x8+x8)
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set PCIE_ENDPOINT_MODE [lindex $pcie_conf_list 2]
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# ------------------------------------------------------------------------------
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# DMA parameters:
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# ------------------------------------------------------------------------------
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# This variable can be set in COREs *.mk file or as a parameter when launching the make
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set DMA_TYPE $env(DMA_TYPE)
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# The minimum number of RX/TX DMA channels for this card is 32.
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set DMA_RX_CHANNELS 32
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set DMA_TX_CHANNELS 32
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# In blocking mode, packets are dropped only when the RX DMA channel is off.
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# In non-blocking mode, packets are dropped whenever they cannot be sent.
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set DMA_RX_BLOCKING_MODE true
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# ------------------------------------------------------------------------------
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# DDR4 parameters:
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# ------------------------------------------------------------------------------
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set MEM_PORTS 0
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# ------------------------------------------------------------------------------
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# Other parameters:
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# ------------------------------------------------------------------------------
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set TSU_ENABLE true

‎cards/silicom/fb2cdg1/config/card_const.tcl‎

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# card_const.tcl: Card specific parameters for Silicom ThunderFjord fb2cdg1 (developer only)
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# Copyright (C) 2025 DynaNIC Semiconductors, Ltd.
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# Author(s): David Beneš <benes@dyna-nic.com>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# WARNING: The user should not deliberately change parameters in this file. For
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# the description of this file, visit the Parametrization section in the
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# documentation of the NDK-CORE repostiory
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set CARD_NAME "FB2CDG1"
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# Achitecture of Clock generator
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set CLOCK_GEN_ARCH "INTEL"
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# Achitecture of PCIe module
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set PCIE_MOD_ARCH "R_TILE"
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# Achitecture of Network module (F_TILE)
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set NET_MOD_ARCH "F_TILE"
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# Achitecture of SDM/SYSMON module
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set SDM_SYSMON_ARCH "INTEL_SDM"
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# Boot controller type (5=OFS_PMCI)
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set BOOT_TYPE 0
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# Total number of QSFP cages
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set QSFP_CAGES 2
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# I2C address of each QSFP cage
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set QSFP_I2C_ADDR(0) "0xA0"
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set QSFP_I2C_ADDR(1) "0xA0"
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# ------------------------------------------------------------------------------
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# Checking of parameter compatibility
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# ------------------------------------------------------------------------------
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if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 0) ||
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($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) )} {
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error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE!
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Allowed PCIe configurations:
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- 1xGen4x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Calypte only)
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- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (for DMA Medusa only)"
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}
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# Enable/add PCIe Gen5 x16 for experiments only!
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#($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) ||
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#- 1xGen5x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0"
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# ------------------------------------------------------------------------------
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# Other parameters:
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# ------------------------------------------------------------------------------
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# Current setup is same for all IP cores, due to use of one pll with frequency (830,156Mhz), for all IP's:
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# This setup value is defined as half of pll frequency
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set TSU_FREQUENCY 415039062

‎cards/silicom/fb2cdg1/constr/bmc.qsf‎

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# bmc.qsf
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# Copyright (C) 2025 DynaNIC Semiconductors, Ltd.
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# Author(s): David Beneš <benes@dyna-nic.com>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# QSPI interface to Flash through BMC:
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set_location_assignment PIN_D29 -to QSPI_CSN_1V2
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set_location_assignment PIN_B31 -to QSPI_CLK
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set_location_assignment PIN_D33 -to QSPI_D0
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set_location_assignment PIN_E32 -to QSPI_D1
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set_location_assignment PIN_B33 -to QSPI_D2
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set_location_assignment PIN_A32 -to QSPI_D3
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# SPI bus from FPGA to BMC (Ingress):
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set_location_assignment PIN_E26 -to SPI_INGRESS_SCLK
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set_location_assignment PIN_E30 -to SPI_INGRESS_MISO
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set_location_assignment PIN_A30 -to SPI_INGRESS_MOSI
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set_location_assignment PIN_B27 -to SPI_INGRESS_CSN
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# SPI bus from BMC to FPGA (Egress):
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set_location_assignment PIN_A24 -to SPI_EGRESS_CSN
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set_location_assignment PIN_B25 -to SPI_EGRESS_MISO
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set_location_assignment PIN_D25 -to SPI_EGRESS_SCLK
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set_location_assignment PIN_E24 -to SPI_EGRESS_MOSI
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# Misc signals between FPGA and BMC:
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set_location_assignment PIN_A26 -to MAX_FPGA_HB_1V2
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set_location_assignment PIN_D27 -to FPGA_MAX_HB
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set_location_assignment PIN_G30 -to FPGA_MAX_THRM_SHTD_N_1V2
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set_location_assignment PIN_H31 -to FPGA_MAX_FPGA_SEU_1V2

‎cards/silicom/fb2cdg1/constr/device.qsf‎

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# device.qsf
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# Copyright (C) 2025 DynaNIC Semiconductors, Ltd.
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# Author(s): David Beneš <benes@dyna-nic.com>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# ==============================================================================
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# Global assignments
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# ==============================================================================
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set_global_assignment -name DEVICE AGMF039R47A2E2VR0
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set_global_assignment -name FAMILY "Agilex 7"

‎cards/silicom/fb2cdg1/constr/general.qsf‎

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# general.qsf
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# Copyright (C) 2025 DynaNIC Semiconductors, Ltd.
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# Author(s): David Beneš <benes@dyna-nic.com>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#AssemblerAssignments
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#=====================
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8"
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set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 3C
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set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
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set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
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#SetupVIDoperation:
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set_global_assignment -name VID_OPERATION_MODE "PMBUS SLAVE"
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set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
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set_global_assignment -name USE_PWRMGT_SDA SDM_IO16
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set_global_assignment -name USE_PWRMGT_ALERT SDM_IO9
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set_global_assignment -name USE_INIT_DONE SDM_IO5
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set_global_assignment -name USE_CONF_DONE SDM_IO12
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set_global_assignment -name USE_HPS_COLD_RESET SDM_IO7
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set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
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set_global_assignment -name GENERATE_COMPRESSED_SOF ON
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# Retimer Fast Forward Assignments
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# ================================
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#set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD ON
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set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
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# set_global_assignment -name OPTIMIZATION_MODE "SUPERIOR PERFORMANCE WITH MAXIMUM PLACEMENT EFFORT"
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# Preserve XCVR channels
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set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
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# ==============================================================================
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# Pinout and IO Standards
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# ==============================================================================
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#100MHz clk
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set_location_assignment PIN_AB57 -to SYSCLK_100_P
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#set_location_assignment PIN_AC56 -to SYSCLK_100_N
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set_instance_assignment -name IO_STANDARD "1.2V TRUE DIFFERENTIAL SIGNALING" -to SYSCLK_100_P
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SYSCLK_100_P
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# ==============================================================================
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# PWR MGMT - Use this if the boot fails
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# ==============================================================================
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# set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888
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# set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 55
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# set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
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# set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
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# set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
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# set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF
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# set_global_assignment -name PWRMGT_PAGE_COMMAND_PAYLOAD 0

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