fix(nvme): map bar

Signed-off-by: Anhad Singh <andypythonappdeveloper@gmail.com>

Author: Andy-Python-Programmer

src/aero_kernel/src/drivers/block/nvme/mod.rs

@@ -29,7 +29,7 @@ use alloc::vec::Vec;
 use bit_field::BitField;
 
 use crate::arch::interrupts::{self, InterruptStack};
-use crate::drivers::pci::*;
+use crate::drivers::pci::{self, *};
 use crate::fs::block::{install_block_device, BlockDevice, BlockDeviceInterface};
 use crate::mem::paging::*;
 
@@ -281,11 +281,13 @@ impl<'a> Controller<'a> {
         let bar0 = header.get_bar(0).ok_or(Error::UnknownBar)?;
 
         // All NVMe registers are accessible via BAR0.
-        let registers_addr = match bar0 {
-            Bar::Memory64 { address, .. } => PhysAddr::new(address),
+        let (registers_addr, bar_size) = match bar0 {
+            Bar::Memory64 { address, size, .. } => (PhysAddr::new(address), size),
             _ => return Err(Error::UnknownBar),
         };
 
+        pci::map_bar(&bar0);
+
         let registers = registers_addr
             .as_hhdm_virt()
             .read_mut::<Registers>()

src/aero_kernel/src/drivers/pci.rs

@@ -23,7 +23,7 @@ use crate::utils::bitmap::Bitmap;
 use crate::utils::sync::Mutex;
 
 use crate::acpi::mcfg;
-use crate::mem::paging::OffsetPageTable;
+use crate::mem::paging::{OffsetPageTable, PhysAddr};
 use crate::utils::VolatileCell;
 
 use crate::arch::{apic, io};
@@ -116,16 +116,18 @@ impl<'a> Msix<'a> {
             .get_bar(bar_index)
             .expect("msix: table bar not present");
 
+        map_bar(&bar);
+
         let bar_address = match bar {
-            Bar::Memory64 { address, .. } => address,
-            Bar::Memory32 { address, .. } => address as u64,
+            Bar::Memory64 { address, .. } => PhysAddr::new(address),
+            Bar::Memory32 { address, .. } => PhysAddr::new(address as u64),
             _ => unreachable!(),
         };
 
         // SAFETY: We have exclusive access to the BAR and the slice is in bounds.
         let messages = unsafe {
             core::slice::from_raw_parts_mut(
-                (bar_address + bar_offset as u64) as *mut Message,
+                (bar_address.as_hhdm_virt() + bar_offset as u64).as_mut_ptr::<Message>(),
                 table_length as usize,
             )
         };
@@ -788,6 +790,45 @@ impl PciTable {
     }
 }
 
+pub fn map_bar(bar: &Bar) {
+    use crate::mem::paging::{Mapper, Page, PageTableFlags, PhysFrame, Size4KiB, UnmapError};
+
+    use crate::mem::AddressSpace;
+
+    let mut address_space = AddressSpace::this();
+    let mut offset_table = address_space.offset_page_table();
+
+    let (addr, size) = match bar {
+        Bar::Memory64 { address, size, .. } => (PhysAddr::new(*address), *size),
+        _ => unreachable!(),
+    };
+
+    for frame in PhysFrame::range(
+        PhysFrame::<Size4KiB>::from_start_address(addr).unwrap(),
+        PhysFrame::containing_address(addr + size),
+    ) {
+        let virt = frame.start_address().as_hhdm_virt();
+        let page = Page::containing_address(virt);
+
+        // Map will fail if the bar was partially mapped.
+        match offset_table.unmap(page) {
+            Ok((_, m)) => m.ignore(),
+            Err(UnmapError::PageNotMapped) => {}
+            Err(e) => unreachable!("{:?}", e),
+        }
+
+        unsafe {
+            offset_table.map_to(
+                page,
+                frame,
+                PageTableFlags::PRESENT | PageTableFlags::WRITABLE | PageTableFlags::NO_EXECUTE,
+            )
+        }
+        .unwrap()
+        .flush();
+    }
+}
+
 pub fn register_device_driver(handle: Arc<dyn PciDeviceHandle>) {
     PCI_TABLE.lock().inner.push(PciDevice { handle })
 }

src/aero_kernel/src/mem/paging/page.rs

@@ -249,6 +249,12 @@ impl<S: PageSize> PhysFrame<S> {
         Ok(PhysFrame::containing_address(address))
     }
 
+    /// Returns a range of pages, exclusive `end`.
+    #[inline]
+    pub const fn range(start: Self, end: Self) -> PhysFrameRange<S> {
+        PhysFrameRange { start, end }
+    }
+
     /// Returns the frame that contains the given physical address.
     #[inline]
     pub fn containing_address(address: PhysAddr) -> Self {