misc(kernel): make clippy happier!

Signed-off-by: Anhad Singh <andypythonappdeveloper@gmail.com>

Author: Andy-Python-Programmer

src/Cargo.lock

@@ -106,14 +106,14 @@ impl Iterator for MadtIterator {
         while self.current < self.limit {
             unsafe {
                 let entry_pointer = self.current;
-                let header = *(self.current as *const EntryHeader);
+                let header = *self.current.cast::<EntryHeader>();
 
                 self.current = self.current.offset(header.length as isize);
 
                 let item = match header.entry_type {
-                    0 => MadtEntry::LocalApic(&*(entry_pointer as *const MadtLocalApic)),
-                    1 => MadtEntry::IoApic(&*(entry_pointer as *const IoApicHeader)),
-                    2 => MadtEntry::IntSrcOverride(&*(entry_pointer as *const MadtIntSrcOverride)),
+                    0 => MadtEntry::LocalApic(&*entry_pointer.cast::<MadtLocalApic>()),
+                    1 => MadtEntry::IoApic(&*entry_pointer.cast::<IoApicHeader>()),
+                    2 => MadtEntry::IntSrcOverride(&*entry_pointer.cast::<MadtIntSrcOverride>()),
 
                     0x10..=0x7f => continue,
                     0x80..=0xff => continue,

src/aero_kernel/src/acpi/madt.rs

@@ -19,6 +19,8 @@ use crate::mem::paging::{PhysAddr, PhysFrame, VirtAddr};
 
 bitflags::bitflags! {
     /// Controls cache settings for the level 4 page table.
+    #[derive(Debug, Copy, Clone)]
+    #[repr(transparent)]
     pub struct Cr3Flags: u64 {
         /// Use a writethrough cache policy for the P4 table (else a writeback policy is used).
         const PAGE_LEVEL_WRITETHROUGH = 1 << 3;
@@ -29,6 +31,8 @@ bitflags::bitflags! {
 
 bitflags::bitflags! {
     /// Controls cache settings for the level 4 page table.
+    #[derive(Debug, Copy, Clone)]
+    #[repr(transparent)]
     pub struct Cr4Flags: u64 {
         /// Enables hardware-supported performance enhancements for software running in
         /// virtual-8086 mode.
@@ -86,6 +90,8 @@ bitflags::bitflags! {
 
 bitflags::bitflags! {
     /// Configuration flags of the [`Cr0`] register.
+    #[derive(Debug, Copy, Clone)]
+    #[repr(transparent)]
     pub struct Cr0Flags: u64 {
         /// Enables protected mode.
         const PROTECTED_MODE_ENABLE = 1;
@@ -184,7 +190,7 @@ bitflags::bitflags! {
 }
 
 bitflags::bitflags! {
-    #[derive(Debug)]
+    #[derive(Debug, Copy, Clone)]
     pub struct MxCsr: u32 {
         const INVALID_OPERATION = 1 << 0;
         const DENORMAL = 1 << 1;
@@ -212,6 +218,7 @@ bitflags::bitflags! {
     /// For MPX, [`BNDREG`](XCr0Flags::BNDREG) and [`BNDCSR`](XCr0Flags::BNDCSR) must be set/unset simultaneously.
     /// For AVX-512, [`OPMASK`](XCr0Flags::OPMASK), [`ZMM_HI256`](XCr0Flags::ZMM_HI256), and [`HI16_ZMM`](XCr0Flags::HI16_ZMM)
     /// must be set/unset simultaneously.
+    #[derive(Debug, Copy, Clone)]
     #[repr(transparent)]
     pub struct XCr0Flags: u64 {
         /// Enables using the x87 FPU state

src/aero_kernel/src/arch/x86_64/controlregs.rs

@@ -31,6 +31,7 @@ use core::ptr::addr_of;
 use alloc::alloc::alloc_zeroed;
 
 bitflags::bitflags! {
+    #[derive(Debug, Copy, Clone)]
     struct GdtEntryFlags: u8 {
         const PROTECTED_MODE = 1 << 6;
         const LONG_MODE = 1 << 5;

src/aero_kernel/src/arch/x86_64/gdt.rs

@@ -367,7 +367,7 @@ impl ArchTask {
     pub fn exec(
         &mut self,
         vm: &Vm,
-        executable: DirCacheItem,
+        executable: &DirCacheItem,
 
         argv: Option<ExecArgs>,
         envv: Option<ExecArgs>,

src/aero_kernel/src/arch/x86_64/task.rs

@@ -233,12 +233,13 @@ impl<'a> Namespace<'a> {
         assert!(size_bytes != 0);
 
         let blocks = size_bytes.div_ceil(self.block_size);
-        let mut read_cmd = ReadWriteCommand::default();
-
-        read_cmd.opcode = opcode as u8;
-        read_cmd.nsid = self.nsid;
-        read_cmd.start_lba = sector as u64;
-        read_cmd.length = (blocks - 1) as u16;
+        let mut read_cmd = ReadWriteCommand {
+            opcode: opcode as u8,
+            nsid: self.nsid,
+            start_lba: sector as u64,
+            length: (blocks - 1) as u16,
+            ..Default::default()
+        };
 
         if size_bytes > Size4KiB::SIZE as usize {
             // The data cannot fit in 8KiB frames, so we need to use
@@ -338,13 +339,18 @@ impl<'a> Controller<'a> {
         registers.set_enable(true)?;
 
         let identity = Dma::<IdentifyController>::zeroed();
-        let mut identify_command = IdentifyCommand::default();
 
-        identify_command.opcode = AdminOpcode::Identify as u8;
-        identify_command.cns = IdentifyCns::Controller as u8;
-        identify_command.data_ptr.prp1 = identity.addr().as_u64();
-
-        admin.submit_command(identify_command);
+        // TODO(andypython): builder pattern for building a command? We also shouldn't be required
+        // to manually fill in the `opcode` field.
+        admin.submit_command(IdentifyCommand {
+            opcode: AdminOpcode::Identify as u8,
+            cns: IdentifyCns::Controller as u8,
+            data_ptr: DataPointer {
+                prp1: identity.addr().as_u64(),
+                ..Default::default()
+            },
+            ..Default::default()
+        });
 
         log::trace!(
             "nvme: identifed controller (vendor={}, subsystem_vendor={})",
@@ -355,27 +361,25 @@ impl<'a> Controller<'a> {
         // Create and initialize the I/O queues.
         let io_queue = QueuePair::new(registers, queue_size)?;
 
-        let mut io_cq_cmd = CreateCQCommand::default();
-
-        io_cq_cmd.opcode = AdminOpcode::CreateCq as u8;
-        io_cq_cmd.prp1 = io_queue.completion_addr().as_u64();
-        io_cq_cmd.cqid = io_queue.id();
-        io_cq_cmd.q_size = (io_queue.len() - 1) as u16;
-        io_cq_cmd.irq_vector = 0;
-        io_cq_cmd.cq_flags = CommandFlags::QUEUE_PHYS_CONTIG.bits();
-
-        admin.submit_command(io_cq_cmd);
-
-        let mut io_sq_cmd = CreateSQCommand::default();
-
-        io_sq_cmd.opcode = AdminOpcode::CreateSq as u8;
-        io_sq_cmd.prp1 = io_queue.submission_addr().as_u64();
-        io_sq_cmd.cqid = io_queue.id();
-        io_sq_cmd.sqid = io_queue.id();
-        io_sq_cmd.q_size = (io_queue.len() - 1) as u16;
-        io_sq_cmd.sq_flags = CommandFlags::QUEUE_PHYS_CONTIG.bits();
+        admin.submit_command(CreateCQCommand {
+            opcode: AdminOpcode::CreateCq as u8,
+            prp1: io_queue.completion_addr().as_u64(),
+            cqid: io_queue.id(),
+            q_size: (io_queue.len() - 1) as u16,
+            irq_vector: 0,
+            cq_flags: CommandFlags::QUEUE_PHYS_CONTIG.bits(),
+            ..Default::default()
+        });
 
-        admin.submit_command(io_sq_cmd);
+        admin.submit_command(CreateSQCommand {
+            opcode: AdminOpcode::CreateSq as u8,
+            prp1: io_queue.submission_addr().as_u64(),
+            cqid: io_queue.id(),
+            sqid: io_queue.id(),
+            q_size: (io_queue.len() - 1) as u16,
+            sq_flags: CommandFlags::QUEUE_PHYS_CONTIG.bits(),
+            ..Default::default()
+        });
 
         let shift = 12 + registers.capability.mpsmin() as usize;
         let max_transfer_shift = if identity.mdts != 0 {
@@ -395,13 +399,16 @@ impl<'a> Controller<'a> {
         // Discover and initialize the namespaces.
         let nsids = {
             let nsid_list = Dma::<u32>::new_uninit_slice(this.identity.nn as usize);
-            let mut nsid_command = IdentifyCommand::default();
 
-            nsid_command.opcode = AdminOpcode::Identify as u8;
-            nsid_command.cns = IdentifyCns::ActivateList as u8;
-            nsid_command.data_ptr.prp1 = nsid_list.addr().as_u64();
-
-            this.admin.lock().submit_command(nsid_command);
+            this.admin.lock().submit_command(IdentifyCommand {
+                opcode: AdminOpcode::Identify as u8,
+                cns: IdentifyCns::ActivateList as u8,
+                data_ptr: DataPointer {
+                    prp1: nsid_list.addr().as_u64(),
+                    ..Default::default()
+                },
+                ..Default::default()
+            });
 
             // SAFETY: The list is initialized above.
             unsafe { nsid_list.assume_init() }
@@ -416,14 +423,17 @@ impl<'a> Controller<'a> {
             }
 
             let identity = Dma::<IdentifyNamespace>::zeroed();
-            let mut identify_command = IdentifyCommand::default();
-
-            identify_command.opcode = AdminOpcode::Identify as u8;
-            identify_command.cns = IdentifyCns::Namespace as u8;
-            identify_command.nsid = nsid;
-            identify_command.data_ptr.prp1 = identity.addr().as_u64();
 
-            this.admin.lock().submit_command(identify_command);
+            this.admin.lock().submit_command(IdentifyCommand {
+                opcode: AdminOpcode::Identify as u8,
+                cns: IdentifyCns::Namespace as u8,
+                nsid,
+                data_ptr: DataPointer {
+                    prp1: identity.addr().as_u64(),
+                    ..Default::default()
+                },
+                ..Default::default()
+            });
 
             let blocks = identity.nsze as usize;
             let block_size = 1 << identity.lbaf[(identity.flbas & 0b11111) as usize].ds;

src/aero_kernel/src/drivers/block/nvme/mod.rs

@@ -1,5 +1,4 @@
 use core::cell::UnsafeCell;
-use core::ptr;
 use core::sync::atomic::{AtomicU16, Ordering};
 
 use crate::mem::paging::PhysAddr;

src/aero_kernel/src/drivers/block/nvme/queue.rs

@@ -613,7 +613,7 @@ impl NetworkDriver for Device {
         loop {
             let mut e1000 = self.e1000.lock_irq();
             if let Some(data) = e1000.recv() {
-                self.wq.remove(task);
+                self.wq.remove(&task);
                 return data;
             } else {
                 drop(e1000);