@@ -296,19 +296,27 @@ bool STM32_EMAC::low_level_init_successful()
296296 EthHandle.Init .RxMode = ETH_RXINTERRUPT_MODE;
297297 EthHandle.Init .ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
298298 EthHandle.Init .MediaInterface = ETH_MEDIA_INTERFACE_RMII;
299- HAL_ETH_Init (&EthHandle);
299+ if (HAL_ETH_Init (&EthHandle) != HAL_OK) {
300+ return false ;
301+ }
300302
301303 /* Initialize Tx Descriptors list: Chain Mode */
302- HAL_ETH_DMATxDescListInit (&EthHandle, DMATxDscrTab, &Tx_Buff[0 ][0 ], ETH_TXBUFNB);
304+ if (HAL_ETH_DMATxDescListInit (&EthHandle, DMATxDscrTab, &Tx_Buff[0 ][0 ], ETH_TXBUFNB) != HAL_OK) {
305+ return false ;
306+ }
303307
304308 /* Initialize Rx Descriptors list: Chain Mode */
305- HAL_ETH_DMARxDescListInit (&EthHandle, DMARxDscrTab, &Rx_Buff[0 ][0 ], ETH_RXBUFNB);
309+ if (HAL_ETH_DMARxDescListInit (&EthHandle, DMARxDscrTab, &Rx_Buff[0 ][0 ], ETH_RXBUFNB) != HAL_OK) {
310+ return false ;
311+ }
306312
307313 /* Configure MAC */
308314 _eth_config_mac (&EthHandle);
309315
310316 /* Enable MAC and DMA transmission and reception */
311- HAL_ETH_Start (&EthHandle);
317+ if (HAL_ETH_Start (&EthHandle) != HAL_OK) {
318+ return false ;
319+ }
312320
313321 return true ;
314322}
@@ -370,7 +378,7 @@ bool STM32_EMAC::low_level_init_successful()
370378bool STM32_EMAC::link_out (emac_mem_buf_t *buf)
371379#ifndef ETH_IP_VERSION_V2
372380{
373- bool success;
381+ bool success = true ;
374382 emac_mem_buf_t *q;
375383 uint8_t *buffer = reinterpret_cast <uint8_t *>(EthHandle.TxDesc ->Buffer1Addr );
376384 __IO ETH_DMADescTypeDef *DmaTxDesc;
@@ -424,9 +432,10 @@ bool STM32_EMAC::link_out(emac_mem_buf_t *buf)
424432 }
425433
426434 /* Prepare transmit descriptors to give to DMA */
427- HAL_ETH_TransmitFrame (&EthHandle, framelength);
435+ if ( HAL_ETH_TransmitFrame (&EthHandle, framelength) != HAL_OK) {
428436
429- success = true ;
437+ success = false ;
438+ }
430439
431440error:
432441
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