STM32 EMAC : more configurable

- PHY default configuration can be changed
  - AutoNegotiation
  - Speed
  - DuplexMode
- PHY register offset can be updated depending on chosen PHY

All unused parameters are cleaned.

Author: jeromecoutant

features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json

@@ -3,9 +3,37 @@
     "config": {
         "eth-rxbufnb": 4,
         "eth-txbufnb": 4,
-        "eth-phyaddr": {
+        "eth-phy-address": {
             "help" : "Configures actual PHY address according to pullup/down status of PHYAD pin(s)",
             "value" : 0
+        },
+        "eth-phy-AutoNegotiation": {
+            "help" : "Selects AutoNegotiation mode : ETH_AUTONEGOTIATION_ENABLE / ETH_AUTONEGOTIATION_DISABLE",
+            "value" : "ETH_AUTONEGOTIATION_ENABLE"
+        },
+        "eth-phy-DuplexMode": {
+            "help" : "Selects DuplexMode mode : ETH_MODE_FULLDUPLEX / ETH_MODE_HALFDUPLEX",
+            "value" : "ETH_MODE_FULLDUPLEX"
+        },
+        "eth-phy-Speed": {
+            "help" : "Selects Speed mode : ETH_SPEED_100M / ETH_SPEED_10M",
+            "value" : "ETH_SPEED_100M"
+        },
+        "eth-phy-reset-delay": {
+            "help" : "Reset process time - Default value: 0.5s as specified in LAN8742A datasheet",
+            "value" : "500"
+        },
+        "eth-phy-status-register": {
+            "help" : "PHY register Offset with auto-negotiation result - Default value is LAN8742A PHY Special Control/Status Register",
+            "value" : "31"
+        },
+        "eth-phy-speed-status": {
+            "help" : "Speed mask information in eth-phy-status-register",
+            "value" : "0x0004"
+        },
+        "eth-phy-duplex-status": {
+            "help" : "Duplex mask information in eth-phy-status-register",
+            "value" : "0x0010"
         }
     },
     "target_overrides": {
@@ -14,7 +42,7 @@
             "eth-txbufnb": 4
         },
         "ARCH_MAX": {
-            "eth-phyaddr": 1
+            "eth-phy-address": 1
         }
     }
 }

features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp

@@ -43,7 +43,6 @@
 #define THREAD_PRIORITY         (osPriorityHigh)
 
 #define PHY_TASK_PERIOD_MS      200
-#define ETH_PHY_ADDRESS         MBED_CONF_STM32_EMAC_ETH_PHYADDR
 
 #define STM_HWADDR_SIZE         (6)
 #define STM_ETH_MTU_SIZE        1500
@@ -279,10 +278,10 @@ bool STM32_EMAC::low_level_init_successful()
     /* Init ETH */
     uint8_t MACAddr[6];
     EthHandle.Instance = ETH;
-    EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
-    EthHandle.Init.Speed = ETH_SPEED_100M;
-    EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
-    EthHandle.Init.PhyAddress = ETH_PHY_ADDRESS;
+    EthHandle.Init.AutoNegotiation = MBED_CONF_STM32_EMAC_ETH_PHY_AUTONEGOTIATION;
+    EthHandle.Init.Speed = MBED_CONF_STM32_EMAC_ETH_PHY_SPEED;
+    EthHandle.Init.DuplexMode = MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEXMODE;
+    EthHandle.Init.PhyAddress = MBED_CONF_STM32_EMAC_ETH_PHY_ADDRESS;
 #if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
     MACAddr[0] = MBED_MAC_ADDR_0;
     MACAddr[1] = MBED_MAC_ADDR_1;

features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.h

@@ -1,4 +1,6 @@
 /* Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017 STMicroelectronics
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -176,4 +178,4 @@ class STM32_EMAC : public EMAC {
     int phy_task_handle; /**< Handle for phy task event */
 };
 
-#endif /* K64F_EMAC_H_ */
+#endif /* STM32_EMAC_H_ */

targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_conf.h

@@ -162,75 +162,52 @@
 
 /* ################## Ethernet peripheral configuration ##################### */
 
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0                         2U
-#define MAC_ADDR1                         0U
-#define MAC_ADDR2                         0U
-#define MAC_ADDR3                         0U
-#define MAC_ADDR4                         0U
-#define MAC_ADDR5                         0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 
 #ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
-#define ETH_RXBUFNB                       MBED_CONF_STM32_EMAC_ETH_RXBUFNB  /* Rx buffers of size ETH_RX_BUF_SIZE  */
-#endif
-
-#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB
-#define ETH_TXBUFNB                       MBED_CONF_STM32_EMAC_ETH_TXBUFNB  /* Tx buffers of size ETH_TX_BUF_SIZE  */
+/* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
+#define ETH_RXBUFNB                    MBED_CONF_STM32_EMAC_ETH_RXBUFNB  /* Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    MBED_CONF_STM32_EMAC_ETH_TXBUFNB  /* Tx buffers of size ETH_TX_BUF_SIZE  */
+#else
+/* ex: bare metal profile */
+#define ETH_RXBUFNB                    0  /* Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    0  /* Tx buffers of size ETH_TX_BUF_SIZE  */
 #endif
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
+/* PHY delay */
+#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
+#define PHY_RESET_DELAY                 MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
+#else
+#define PHY_RESET_DELAY                 0
+#endif
 #define PHY_CONFIG_DELAY                0x00000FFFU
-
 #define PHY_READ_TO                     0x0000FFFFU
 #define PHY_WRITE_TO                    0x0000FFFFU
 
 /* Section 3: Common PHY Registers */
 
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
+#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */
 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
 
 /* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
+#define PHY_SR                          MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER  /*!< PHY status register Offset                      */
+#define PHY_SPEED_STATUS                MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS     /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS    /*!< PHY Duplex mask                                 */
+#else
+#define PHY_SR                          0
+#define PHY_SPEED_STATUS                0
+#define PHY_DUPLEX_STATUS               0
+#endif
 
 /* ################## SPI peripheral configuration ########################## */
 

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h

@@ -170,75 +170,52 @@
 
 /* ################## Ethernet peripheral configuration ##################### */
 
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
 /* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 
 #ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
-#define ETH_RXBUFNB                       MBED_CONF_STM32_EMAC_ETH_RXBUFNB  /* Rx buffers of size ETH_RX_BUF_SIZE  */
-#endif
-
-#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB
-#define ETH_TXBUFNB                       MBED_CONF_STM32_EMAC_ETH_TXBUFNB  /* Tx buffers of size ETH_TX_BUF_SIZE  */
+/* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
+#define ETH_RXBUFNB                    MBED_CONF_STM32_EMAC_ETH_RXBUFNB  /* Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    MBED_CONF_STM32_EMAC_ETH_TXBUFNB  /* Tx buffers of size ETH_TX_BUF_SIZE  */
+#else
+/* ex: bare metal profile */
+#define ETH_RXBUFNB                    0  /* Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    0  /* Tx buffers of size ETH_TX_BUF_SIZE  */
 #endif
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
+/* PHY delay */
+#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
+#define PHY_RESET_DELAY                 MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
+#else
+#define PHY_RESET_DELAY                 0
+#endif
 #define PHY_CONFIG_DELAY                0x00000FFFU
-
 #define PHY_READ_TO                     0x0000FFFFU
 #define PHY_WRITE_TO                    0x0000FFFFU
 
 /* Section 3: Common PHY Registers */
 
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
+#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+  
 /* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
+#define PHY_SR                          MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER  /*!< PHY status register Offset                      */
+#define PHY_SPEED_STATUS                MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS     /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS    /*!< PHY Duplex mask                                 */
+#else
+#define PHY_SR                          0
+#define PHY_SPEED_STATUS                0
+#define PHY_DUPLEX_STATUS               0
+#endif
 
 /* ################## SPI peripheral configuration ########################## */