44 */
55
66/* ****************************************************************************
7- * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
7+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
88 *
99 * Permission is hereby granted, free of charge, to any person obtaining a
1010 * copy of this software and associated documentation files (the "Software"),
4242/* **** Includes **** */
4343#include <stdbool.h>
4444#include "mxc_device.h"
45- #include "mxc_errors.h"
4645#include "dma_regs.h"
4746
4847#ifdef __cplusplus
@@ -57,63 +56,75 @@ extern "C" {
5756
5857/* **** Definitions **** */
5958
60-
6159/**
6260 * @brief Enumeration for the DMA Channel's priority level.
6361 *
6462 */
6563typedef enum {
66- MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH , ///< High Priority */
67- MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH , ///< Medium High Priority */
68- MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW , ///< Medium Low Priority */
69- MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW , ///< Low Priority */
64+ MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH , ///< High Priority */
65+ MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH , ///< Medium High Priority */
66+ MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW , ///< Medium Low Priority */
67+ MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW , ///< Low Priority */
7068} mxc_dma_priority_t ;
7169
7270/** @brief DMA request select */
7371typedef enum {
74- MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM , ///< Memory to Memory DMA Request Selection
75- MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX , ///< SPI0 Receive DMA Request Selection
76- MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX , ///< SPI1 Receive DMA Request Selection
77- MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX , ///< UART0 Receive DMA Request Selection
78- MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX , ///< UART1 Receive DMA Request Selection
79- MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX , ///< I2C0 Receive DMA Request Selection
80- MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX , ///< I2C1 Receive DMA Request Selection
81- MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX , ///< SPI0 Transmit DMA Request Selection
82- MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX , ///< SPI1 Transmit DMA Request Selection
83- MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX , ///< UART0 Transmit DMA Request Selection
84- MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX , ///< UART1 Transmit DMA Request Selection
85- MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX , ///< I2C0 Transmit DMA Request Selection
86- MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX , ///< I2C1 Transmit DMA Request Selection
72+ MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM , ///< Memory to Memory DMA Request Selection
73+ MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX , ///< SPI0 Receive DMA Request Selection
74+ MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX , ///< SPI1 Receive DMA Request Selection
75+ MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX , ///< SPI2 Receive DMA Request Selection
76+ MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CTRL_REQUEST_UART0RX , ///< UART0 Receive DMA Request Selection
77+ MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CTRL_REQUEST_UART1RX , ///< UART1 Receive DMA Request Selection
78+ MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX , ///< I2C0 Receive DMA Request Selection
79+ MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX , ///< I2C1 Receive DMA Request Selection
80+ MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX , ///< I2C2 Receive DMA Request Selection
81+ MXC_DMA_REQUEST_UART2RX = MXC_S_DMA_CTRL_REQUEST_UART2RX , ///< UART2 Receive DMA Request Selection
82+ MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX , ///< AES Receive DMA Request Selection
83+ MXC_DMA_REQUEST_UART3RX = MXC_S_DMA_CTRL_REQUEST_UART3RX , ///< UART3 Receive DMA Request Selection
84+ MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX , ///< I2S Receive DMA Request Selection
85+ MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX , ///< SPI0 Transmit DMA Request Selection
86+ MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX , ///< SPI1 Transmit DMA Request Selection
87+ MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX , ///< SPI2 Transmit DMA Request Selection
88+ MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CTRL_REQUEST_UART0TX , ///< UART0 Transmit DMA Request Selection
89+ MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CTRL_REQUEST_UART1TX , ///< UART1 Transmit DMA Request Selection
90+ MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX , ///< I2C0 Transmit DMA Request Selection
91+ MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX , ///< I2C1 Transmit DMA Request Selection
92+ MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX , ///< I2C2 Transmit DMA Request Selection
93+ MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX , ///< CRC Transmit DMA Request Selection
94+ MXC_DMA_REQUEST_UART2TX = MXC_S_DMA_CTRL_REQUEST_UART2TX , ///< UART2 Transmit DMA Request Selection
95+ MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX , ///< AES Transmit DMA Request Selection
96+ MXC_DMA_REQUEST_UART3TX = MXC_S_DMA_CTRL_REQUEST_UART3TX , ///< UART3 Transmit DMA Request Selection
97+ MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX , ///< I2S Transmit DMA Request Selection
8798} mxc_dma_reqsel_t ;
8899
89100/** @brief Enumeration for the DMA prescaler */
90101typedef enum {
91- MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS , ///< Prescaler disabled
92- MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256 , ///< Divide by 256
93- MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K , ///< Divide by 65,536
94- MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M , ///< Divide by 16,777,216
102+ MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS , ///< Prescaler disabled
103+ MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 , ///< Divide by 256
104+ MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K , ///< Divide by 65,536
105+ MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M , ///< Divide by 16,777,216
95106} mxc_dma_prescale_t ;
96107
97108/** @brief Enumeration for the DMA timeout value */
98109typedef enum {
99- MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4 , ///< DMA timeout of 4 clocks
100- MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8 , ///< DMA timeout of 8 clocks
101- MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16 , ///< DMA timeout of 16 clocks
102- MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32 , ///< DMA timeout of 32 clocks
103- MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64 , ///< DMA timeout of 64 clocks
104- MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128 , ///< DMA timeout of 128 clocks
105- MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256 , ///< DMA timeout of 256 clocks
106- MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512 , ///< DMA timeout of 512 clocks
110+ MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4 , ///< DMA timeout of 4 clocks
111+ MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8 , ///< DMA timeout of 8 clocks
112+ MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16 , ///< DMA timeout of 16 clocks
113+ MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32 , ///< DMA timeout of 32 clocks
114+ MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64 , ///< DMA timeout of 64 clocks
115+ MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128 , ///< DMA timeout of 128 clocks
116+ MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256 , ///< DMA timeout of 256 clocks
117+ MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512 , ///< DMA timeout of 512 clocks
107118} mxc_dma_timeout_t ;
108119
109120/** @brief DMA transfer data width */
110121typedef enum {
111122 /* Using the '_V_' define instead of the '_S_' since these same values will be used to
112123 specify the DSTWD also. The API functions will shift the value the correct amount
113124 prior to writing the cfg register. */
114- MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE , ///< DMA transfer in bytes
115- MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD , ///< DMA transfer in 16-bit half-words
116- MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD , ///< DMA transfer in 32-bit words
125+ MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE , ///< DMA transfer in bytes
126+ MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD , ///< DMA transfer in 16-bit half-words
127+ MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD , ///< DMA transfer in 32-bit words
117128} mxc_dma_width_t ;
118129
119130/**
@@ -246,7 +257,7 @@ int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst);
246257 *
247258 * @return See \ref MXC_Error_Codes for a list of return values
248259 */
249- int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t * srcdst );
260+ int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t * srcdst );
250261
251262/**
252263 * @brief Set channel reload source, destination, and count for the transfer
@@ -266,7 +277,7 @@ int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
266277 *
267278 * @return See \ref MXC_Error_Codes for a list of return values
268279 */
269- int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t * srcdstReload );
280+ int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t * srcdstReload );
270281
271282/**
272283 * @brief Set channel interrupt callback
@@ -302,7 +313,7 @@ int MXC_DMA_SetCallback (int ch, void (*callback) (int, int));
302313 * @param ctz Enable channel count to zero interrupt.
303314 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
304315 */
305- int MXC_DMA_SetChannelInterruptEn (int ch , bool chdis , bool ctz );
316+ int MXC_DMA_SetChannelInterruptEn (int ch , bool chdis , bool ctz );
306317
307318/**
308319 * @brief Enable channel interrupt
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