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Add peripheral interface files
Signed-off-by: Sadik.Ozer <Sadik.Ozer@maximintegrated.com>
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/**
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* @file crc.h
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* @brief cyclic redundancy check driver.
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*/
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/* ****************************************************************************
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* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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*************************************************************************** */
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#ifndef _CRC_H_
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#define _CRC_H_
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/***** Includes *****/
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#include "crc_regs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup crc CRC
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* @ingroup periphlibs
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* @{
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*/
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/***** CRC Definitions *****/
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/**
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* @brief Structure used to set up CRC request
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*
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*/
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typedef struct _mxc_crc_req_t {
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uint32_t* dataBuffer; ///< Pointer to the data
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uint32_t dataLen; ///< Length of the data
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uint32_t resultCRC; ///< Calculated CRC value
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} mxc_crc_req_t;
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/**
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* @brief CRC data bit order
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*
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*/
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typedef enum {
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CRC_LSB_FIRST,
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CRC_MSB_FIRST
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} mxc_crc_bitorder_t;
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/***** Function Prototypes *****/
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/* ************************************************************************* */
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/* Global Control/Configuration functions */
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/* ************************************************************************* */
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/**
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* @brief Enable portions of the CRC
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*
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*
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* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
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*/
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int MXC_CRC_Init (void);
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/**
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* @brief Disable and reset portions of the CRC
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*
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* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
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*/
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int MXC_CRC_Shutdown (void);
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/**
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* @brief This function should be called from the CRC ISR Handler
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* when using Async functions
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* @param ch DMA channel
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* @param error error
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*/
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void MXC_CRC_Handler (int ch, int error);
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/**
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* @brief Set the bit-order of CRC calculation
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*
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* @param bitOrder The direction to perform CRC calculation in
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*/
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void MXC_CRC_SetDirection (mxc_crc_bitorder_t bitOrder);
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/**
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* @brief Set the bit-order of CRC calculation
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*
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* @return The direction of calculation, 1 for MSB first, 0 for LSB first
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*/
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mxc_crc_bitorder_t MXC_CRC_GetDirection (void);
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/**
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* @brief Byte Swap CRC Data Input
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*
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* @param bitOrder The direction to perform CRC calculation in
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*/
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void MXC_CRC_SwapDataIn (mxc_crc_bitorder_t bitOrder);
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/**
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* @brief Byte Swap CRC Data output
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*
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* @param bitOrder The direction to perform CRC calculation in
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*/
130+
void MXC_CRC_SwapDataOut (mxc_crc_bitorder_t bitOrder);
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/**
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* @brief Set the Polynomial for CRC calculation
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*
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* @param poly The polynomial to use for CRC calculation
136+
*/
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void MXC_CRC_SetPoly (uint32_t poly);
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/**
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* @brief Get the polynomial for CRC calculation
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*
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* @return The polynomial used in calculation
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*/
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uint32_t MXC_CRC_GetPoly (void);
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/**
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* @brief Get the result of a CRC calculation
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*
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* @return The calculated CRC value
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*/
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uint32_t MXC_CRC_GetResult (void);
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/*******************************/
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/* High Level Functions */
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/*******************************/
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/**
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* @brief Perform a CRC computation
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* @note The result of the CRC calculation will be placed in the
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* mxc_crc_req_t structure
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*
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* @param req Structure containing the data for calculation
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*
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* @return see \ref MXC_Error_Codes for a list of return codes.
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*/
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int MXC_CRC_Compute (mxc_crc_req_t* req);
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/**
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* @brief Perform a CRC computation using DMA
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* @note The result of the CRC calculation will be placed in the
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* mxc_crc_req_t structure. The user must call
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* MXC_DMA_Handler() in the ISR
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*
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* @param req Structure containing the data for calculation
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*
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* @return see \ref MXC_Error_Codes for a list of return codes.
177+
*/
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int MXC_CRC_ComputeAsync (mxc_crc_req_t* req);
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#ifdef __cplusplus
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}
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#endif
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/**@} end of group crc */
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#endif /* _CRC_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h

Lines changed: 49 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
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*/
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/* ****************************************************************************
7-
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
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* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
@@ -42,7 +42,6 @@
4242
/* **** Includes **** */
4343
#include <stdbool.h>
4444
#include "mxc_device.h"
45-
#include "mxc_errors.h"
4645
#include "dma_regs.h"
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4847
#ifdef __cplusplus
@@ -57,63 +56,75 @@ extern "C" {
5756

5857
/* **** Definitions **** */
5958

60-
6159
/**
6260
* @brief Enumeration for the DMA Channel's priority level.
6361
*
6462
*/
6563
typedef enum {
66-
MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH, ///< High Priority */
67-
MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH, ///< Medium High Priority */
68-
MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW, ///< Medium Low Priority */
69-
MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW, ///< Low Priority */
64+
MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority */
65+
MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority */
66+
MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority */
67+
MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority */
7068
} mxc_dma_priority_t;
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7270
/** @brief DMA request select */
7371
typedef enum {
74-
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection
75-
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection
76-
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection
77-
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection
78-
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, ///< UART1 Receive DMA Request Selection
79-
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, ///< I2C0 Receive DMA Request Selection
80-
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection
81-
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection
82-
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection
83-
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection
84-
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection
85-
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection
86-
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection
72+
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection
73+
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection
74+
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection
75+
MXC_DMA_REQUEST_SPI2RX = MXC_S_DMA_CTRL_REQUEST_SPI2RX, ///< SPI2 Receive DMA Request Selection
76+
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection
77+
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection
78+
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection
79+
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection
80+
MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection
81+
MXC_DMA_REQUEST_UART2RX = MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection
82+
MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection
83+
MXC_DMA_REQUEST_UART3RX = MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection
84+
MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection
85+
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection
86+
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection
87+
MXC_DMA_REQUEST_SPI2TX = MXC_S_DMA_CTRL_REQUEST_SPI2TX, ///< SPI2 Transmit DMA Request Selection
88+
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection
89+
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection
90+
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection
91+
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection
92+
MXC_DMA_REQUEST_I2C2TX = MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection
93+
MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection
94+
MXC_DMA_REQUEST_UART2TX = MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection
95+
MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection
96+
MXC_DMA_REQUEST_UART3TX = MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection
97+
MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection
8798
} mxc_dma_reqsel_t;
8899

89100
/** @brief Enumeration for the DMA prescaler */
90101
typedef enum {
91-
MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, ///< Prescaler disabled
92-
MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, ///< Divide by 256
93-
MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, ///< Divide by 65,536
94-
MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, ///< Divide by 16,777,216
102+
MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled
103+
MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256
104+
MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536
105+
MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216
95106
} mxc_dma_prescale_t;
96107

97108
/** @brief Enumeration for the DMA timeout value */
98109
typedef enum {
99-
MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, ///< DMA timeout of 4 clocks
100-
MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, ///< DMA timeout of 8 clocks
101-
MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, ///< DMA timeout of 16 clocks
102-
MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, ///< DMA timeout of 32 clocks
103-
MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, ///< DMA timeout of 64 clocks
104-
MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, ///< DMA timeout of 128 clocks
105-
MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, ///< DMA timeout of 256 clocks
106-
MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, ///< DMA timeout of 512 clocks
110+
MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks
111+
MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks
112+
MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks
113+
MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks
114+
MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks
115+
MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks
116+
MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks
117+
MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks
107118
} mxc_dma_timeout_t;
108119

109120
/** @brief DMA transfer data width */
110121
typedef enum {
111122
/* Using the '_V_' define instead of the '_S_' since these same values will be used to
112123
specify the DSTWD also. The API functions will shift the value the correct amount
113124
prior to writing the cfg register. */
114-
MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, ///< DMA transfer in bytes
115-
MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words
116-
MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, ///< DMA transfer in 32-bit words
125+
MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes
126+
MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words
127+
MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words
117128
} mxc_dma_width_t;
118129

119130
/**
@@ -246,7 +257,7 @@ int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst);
246257
*
247258
* @return See \ref MXC_Error_Codes for a list of return values
248259
*/
249-
int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t *srcdst);
260+
int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t* srcdst);
250261

251262
/**
252263
* @brief Set channel reload source, destination, and count for the transfer
@@ -266,7 +277,7 @@ int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
266277
*
267278
* @return See \ref MXC_Error_Codes for a list of return values
268279
*/
269-
int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t *srcdstReload);
280+
int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t* srcdstReload);
270281

271282
/**
272283
* @brief Set channel interrupt callback
@@ -302,7 +313,7 @@ int MXC_DMA_SetCallback (int ch, void (*callback) (int, int));
302313
* @param ctz Enable channel count to zero interrupt.
303314
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
304315
*/
305-
int MXC_DMA_SetChannelInterruptEn (int ch, bool chdis, bool ctz);
316+
int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
306317

307318
/**
308319
* @brief Enable channel interrupt

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
*/
66

77
/* ****************************************************************************
8-
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
8+
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
99
*
1010
* Permission is hereby granted, free of charge, to any person obtaining a
1111
* copy of this software and associated documentation files (the "Software"),
@@ -43,7 +43,6 @@
4343
/* **** Includes **** */
4444
#include "flc_regs.h"
4545
#include "mxc_sys.h"
46-
#include "mxc_errors.h"
4746

4847
#ifdef __cplusplus
4948
extern "C" {

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