SOC: Infineon: Add support for CYW20829 B1 revision.

boards/infineon/cyw920829m2evk_02/Kconfig.cyw920829m2evk_02

@@ -4,4 +4,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_CYW920829M2EVK_02
-	select SOC_CYW20829B0LKML
+	select SOC_CYW20829B0LKML if BOARD_CYW920829M2EVK_02_CYW20829B0LKML
+	select SOC_CYW20829B1010 if BOARD_CYW920829M2EVK_02_CYW20829B1010
+	select SOC_CYW20829B1340 if BOARD_CYW920829M2EVK_02_CYW20829B1340

boards/infineon/cyw920829m2evk_02/board.yml

@@ -1,6 +1,13 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
 board:
   name: cyw920829m2evk_02
   full_name: CYW920829M2EVK-02
   vendor: infineon
   socs:
-  - name: cyw20829b0lkml
+    - name: cyw20829b0lkml
+    - name: cyw20829b1010
+    - name: cyw20829b1340

boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-memory_map.dtsi

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <zephyr/dt-bindings/misc/ifx_cyw20829.h>
+
+/ {
+	sram0: memory@20000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "mmio-sram";
+		reg = <SRAM0_SAHB_BASE SRAM0_SIZE>;
+
+		/* SRAM aliased address path */
+		sram_sahb: sram_sahb@20000000 {
+			reg = <SRAM0_SAHB_BASE SRAM0_SIZE>;  /* SAHB address */
+		};
+
+		sram_cbus: sram_cbus@4000000 {
+			reg = <SRAM0_CBUS_BASE SRAM0_SIZE>;  /* CBUS address */
+		};
+	};
+
+	/* sram_bootstrap address calculation:
+	 * sram_sahb + sram_size (256k) - bootstrap size
+	 * (e.g. 0x20000000 + 0x40000 - 16K (0x4000) = 0x2003C000)
+	 */
+	sram_bootstrap: memory@2003c000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "zephyr,memory-region", "mmio-sram";
+		zephyr,memory-region = "BOOTSTRAP_RAM";
+		reg = <BOOTSTRAP_SAHB_BASE BOOTSTRAP_SIZE>;
+
+		/* SRAM aliased address path */
+		sram_bootstrap_sahb: sram_bootstrap_sahb@2003c000 {
+			reg = <BOOTSTRAP_SAHB_BASE BOOTSTRAP_SIZE>;  /* SAHB address */
+		};
+
+		sram_bootstrap_cbus: sram_bootstrap_cbus@403c000 {
+			reg = <BOOTSTRAP_CBUS_BASE BOOTSTRAP_SIZE>;  /* CBUS address */
+		};
+	};
+};
+
+/* Flash Memory Partitioning is defined here.
+ *
+ * Note that the flash memory is located in different locations for different
+ * parts in the family.  For the following parts, flash is located inside the
+ * SOC package but still accessed via the qspi interface.
+ *     - CYW20829B1340
+ *     - CYW20829B1240
+ *     - CYW89829B0232
+ *     - CYW89829B1232
+ *
+ * For other parts in the family, flash is external to the part.  For the
+ * CYW920829M2EVK_02 board, the flash is located on the processor board
+ * (CYW920829M2IPA2) these parts.
+ */
+&flash0 {
+	bootstrap_region: bootstrap_region@0 {
+		reg = <0 BOOTSTRAP_SIZE>;
+	};
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 0x20000>;
+			read-only;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 0x60000>;
+		};
+
+		slot1_partition: partition@80000 {
+			label = "image-1";
+			reg = <0x80000 0x60000>;
+		};
+
+		storage_partition: storage_partition@E0000 {
+			compatible = "soc-nv-flash";
+			reg = <0xE0000 DT_SIZE_K(64)>;
+		};
+	};
+};

boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dtsi

@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/infineon/cat1b/cyw20829/system_clocks.dtsi>
+#include "cyw920829m2evk_02-memory_map.dtsi"
+#include "cyw920829m2evk_02-common.dtsi"
+#include "cyw920829m2evk_02-pinctrl.dtsi"
+
+/ {
+	aliases {
+		watchdog0 = &watchdog0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+		zephyr,bt-hci = &bluetooth;
+	};
+};
+
+uart2: &scb2 {
+	compatible = "infineon,cat1-uart";
+	status = "okay";
+	current-speed = <115200>;
+	hw-flow-control;
+
+	pinctrl-0 = <&p3_3_scb2_uart_tx &p3_2_scb2_uart_rx &p3_1_scb2_uart_rts &p3_0_scb2_uart_cts>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 8>, <&dma0 9>;
+	dma-names = "tx", "rx";
+};
+
+&dma0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "infineon,cat1-dma";
+	status = "okay";
+};
+
+&fll0 {
+	status = "okay";
+};
+
+&path_mux0 {
+	status = "okay";
+};
+
+&path_mux1 {
+	status = "okay";
+};
+
+&path_mux2 {
+	status = "okay";
+};
+
+&path_mux3 {
+	status = "okay";
+};
+
+&clk_hf0 {
+	status = "okay";
+	clocks = <&fll0>;
+};
+
+&clk_hf1 {
+	status = "okay";
+};
+
+&clk_hf2 {
+	status = "okay";
+};
+
+&clk_hf3 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&mcwdt0 {
+	status = "okay";
+};
+
+&bluetooth {
+	status = "okay";
+};

boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_cyw20829b0lkml.dts

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm/infineon/cat1b/mpns/cyw20829b0lkml.dtsi>
+#include "cyw920829m2ipa2.dtsi"
+#include "cyw920829m2evk_02.dtsi"
+
+/ {
+	model = "The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit w/ CYW20829B0LKML";
+	compatible = "infineon,cyw920829m2evk_02", "infineon,CYW20829";
+};