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Boards: Infineon: cyw920829m2evk_02: Reorganizing board hardware
Reorganizing board hardware definition in the device tree to better reflect hardware design of separate processor board and base board. Signed-off-by: John Batch <john.batch@infineon.com>
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‎boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-memory_map.dtsi‎

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/*
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* Copyright (c) 2025 Infineon Technologies AG,
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* or an affiliate of Infineon Technologies AG.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <zephyr/dt-bindings/misc/ifx_cyw20829.h>
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/ {
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sram0: memory@20000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mmio-sram";
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reg = <SRAM0_SAHB_BASE SRAM0_SIZE>;
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/* SRAM aliased address path */
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sram_sahb: sram_sahb@20000000 {
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reg = <SRAM0_SAHB_BASE SRAM0_SIZE>; /* SAHB address */
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};
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sram_cbus: sram_cbus@4000000 {
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reg = <SRAM0_CBUS_BASE SRAM0_SIZE>; /* CBUS address */
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};
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};
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/* sram_bootstrap address calculation:
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* sram_sahb + sram_size (256k) - bootstrap size
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* (e.g. 0x20000000 + 0x40000 - 16K (0x4000) = 0x2003C000)
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*/
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sram_bootstrap: memory@2003c000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "zephyr,memory-region", "mmio-sram";
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zephyr,memory-region = "BOOTSTRAP_RAM";
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reg = <BOOTSTRAP_SAHB_BASE BOOTSTRAP_SIZE>;
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/* SRAM aliased address path */
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sram_bootstrap_sahb: sram_bootstrap_sahb@2003c000 {
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reg = <BOOTSTRAP_SAHB_BASE BOOTSTRAP_SIZE>; /* SAHB address */
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};
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sram_bootstrap_cbus: sram_bootstrap_cbus@403c000 {
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reg = <BOOTSTRAP_CBUS_BASE BOOTSTRAP_SIZE>; /* CBUS address */
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};
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};
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};
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/* Flash Memory Partitioning is defined here.
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*
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* Note that the flash memory is located in different locations for different
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* parts in the family. For the following parts, flash is located inside the
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* SOC package but still accessed via the qspi interface.
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* - CYW20829B1340
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* - CYW20829B1240
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* - CYW89829B0232
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* - CYW89829B1232
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*
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* For other parts in the family, flash is external to the part. For the
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* CYW920829M2EVK_02 board, the flash is located on the processor board
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* (CYW920829M2IPA2) these parts.
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*/
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&flash0 {
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bootstrap_region: bootstrap_region@0 {
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reg = <0 BOOTSTRAP_SIZE>;
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};
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 0x20000>;
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read-only;
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};
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slot0_partition: partition@20000 {
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label = "image-0";
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reg = <0x20000 0x60000>;
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};
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slot1_partition: partition@80000 {
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label = "image-1";
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reg = <0x80000 0x60000>;
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};
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storage_partition: storage_partition@E0000 {
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compatible = "soc-nv-flash";
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reg = <0xE0000 DT_SIZE_K(64)>;
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};
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};
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};

‎boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts‎

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‎boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dtsi‎

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/*
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* Copyright (c) 2025 Infineon Technologies AG,
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* or an affiliate of Infineon Technologies AG.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/infineon/cat1b/cyw20829/system_clocks.dtsi>
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#include "cyw920829m2evk_02-memory_map.dtsi"
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#include "cyw920829m2evk_02-common.dtsi"
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#include "cyw920829m2evk_02-pinctrl.dtsi"
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/ {
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aliases {
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watchdog0 = &watchdog0;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot0_partition;
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zephyr,console = &uart2;
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zephyr,shell-uart = &uart2;
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zephyr,bt-hci = &bluetooth;
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};
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};
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uart2: &scb2 {
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compatible = "infineon,cat1-uart";
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status = "okay";
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current-speed = <115200>;
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hw-flow-control;
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pinctrl-0 = <&p3_3_scb2_uart_tx &p3_2_scb2_uart_rx &p3_1_scb2_uart_rts &p3_0_scb2_uart_cts>;
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pinctrl-names = "default";
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dmas = <&dma0 8>, <&dma0 9>;
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dma-names = "tx", "rx";
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};
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&dma0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "infineon,cat1-dma";
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status = "okay";
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};
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&fll0 {
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status = "okay";
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};
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&path_mux0 {
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status = "okay";
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};
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&path_mux1 {
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status = "okay";
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};
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&path_mux2 {
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status = "okay";
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};
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&path_mux3 {
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status = "okay";
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};
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&clk_hf0 {
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status = "okay";
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clocks = <&fll0>;
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};
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&clk_hf1 {
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status = "okay";
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};
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&clk_hf2 {
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status = "okay";
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};
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&clk_hf3 {
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status = "okay";
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};
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&watchdog0 {
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status = "okay";
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};
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&mcwdt0 {
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status = "okay";
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};
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&bluetooth {
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status = "okay";
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};

‎boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_cyw20829b0lkml.dts‎

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/*
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* Copyright (c) 2025 Infineon Technologies AG,
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* or an affiliate of Infineon Technologies AG.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm/infineon/cat1b/mpns/cyw20829b0lkml.dtsi>
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#include "cyw920829m2ipa2.dtsi"
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#include "cyw920829m2evk_02.dtsi"
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/ {
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model = "The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02) Featuring CYW20829B0LKML";
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compatible = "infineon,cyw920829m2evk_02", "infineon,CYW20829";
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};

‎boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml‎ renamed to ‎boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_cyw20829b0lkml.yaml‎

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#
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# Copyright (c) 2024 Cypress Semiconductor Corporation.
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2025 Infineon Technologies AG,
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# or an affiliate of Infineon Technologies AG.
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#
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# SPDX-License-Identifier: Apache-2.0
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identifier: cyw920829m2evk_02
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name: The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02)
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name: The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02) Featuring CYW20829B0LKML
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type: mcu
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arch: arm
1011
ram: 1024

‎boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig‎ renamed to ‎boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_cyw20829b0lkml_defconfig‎

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# Copyright (c) 2025 Infineon Technologies AG,
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# or an affiliate of Infineon Technologies AG.
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#
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# Copyright (c) 2024 Cypress Semiconductor Corporation.
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# SPDX-License-Identifier: Apache-2.0
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#
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# General configuration
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CONFIG_ARM_MPU=y

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