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1 parent 74bea00 commit 926efb8Copy full SHA for 926efb8
arch/xtensa/core/vector_handlers.c
@@ -468,7 +468,7 @@ __unused static void xtensa_handle_irq_lvl(int irq_lvl)
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#if XCHAL_NUM_INTERRUPTS > 64
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__asm__ volatile("rsr.interrupt2 %0" : "=r"(irq_mask));
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- __asm__ volatile("rsr.intenable2 %0" : "=r"(intenable2));
+ __asm__ volatile("rsr.intenable2 %0" : "=r"(intenable));
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irq_mask &= intenable;
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irq_mask &= xtensa_lvl_mask[irq_lvl - 1][2];
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while (irq_mask) {
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