@@ -39,7 +39,8 @@ int arch_dcache_invd_range(void *addr_in, size_t size)
3939 __asm__ volatile (
4040 "fence\n"
4141 );
42- for (uintptr_t i = addr ; i < addr + size ; i += CONFIG_DCACHE_LINE_SIZE ) {
42+ for (uintptr_t i = addr ; i < ROUND_UP (addr + size , CONFIG_DCACHE_LINE_SIZE );
43+ i += CONFIG_DCACHE_LINE_SIZE ) {
4344 arch_cache_invalidate_dcache_line (i );
4445 }
4546 __asm__ volatile (
@@ -83,7 +84,8 @@ int arch_icache_invd_range(void *addr_in, size_t size)
8384 "fence\n"
8485 "fence.i\n"
8586 );
86- for (uintptr_t i = addr ; i < addr + size ; i += CONFIG_ICACHE_LINE_SIZE ) {
87+ for (uintptr_t i = addr ; i < ROUND_UP (addr + size , CONFIG_ICACHE_LINE_SIZE );
88+ i += CONFIG_ICACHE_LINE_SIZE ) {
8789 arch_cache_invalidate_icache_line (i );
8890 }
8991 __asm__ volatile (
@@ -125,7 +127,8 @@ int arch_dcache_flush_range(void *addr_in, size_t size)
125127 __asm__ volatile (
126128 "fence\n"
127129 );
128- for (uintptr_t i = addr ; i < addr + size ; i += CONFIG_DCACHE_LINE_SIZE ) {
130+ for (uintptr_t i = addr ; i < ROUND_UP (addr + size , CONFIG_DCACHE_LINE_SIZE );
131+ i += CONFIG_DCACHE_LINE_SIZE ) {
129132 arch_cache_clean_dcache_line (i );
130133 }
131134 __asm__ volatile (
@@ -166,7 +169,8 @@ int arch_dcache_flush_and_invd_range(void *addr_in, size_t size)
166169 __asm__ volatile (
167170 "fence\n"
168171 );
169- for (uintptr_t i = addr ; i < addr + size ; i += CONFIG_DCACHE_LINE_SIZE ) {
172+ for (uintptr_t i = addr ; i < ROUND_UP (addr + size , CONFIG_DCACHE_LINE_SIZE );
173+ i += CONFIG_DCACHE_LINE_SIZE ) {
170174 arch_cache_clean_invalidate_dcache_line (i );
171175 }
172176 __asm__ volatile (
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