soc: nordic: vpr: align ESF_SW_IRQ_SIZEOF when new exception debug is used

There is new exception debugging mechanism for RISC-V which needs
additional member in arch_esf structure. VPRs handle stacking
partially in hw so exact position of some stack members needs
to be at the end of arch_esf, so explicit padding is needed.
Aligned also ESF_SW_IRQ_SIZEOF when exception debug is used.

Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>

Author: lstnl

soc/nordic/common/vpr/soc_isr_stacking.h

@@ -15,7 +15,15 @@
 #define VPR_CPU DT_INST(0, nordic_vpr)
 
 #ifdef CONFIG_EXCEPTION_DEBUG
-#define ESF_CSF _callee_saved_t *csf
+/*
+ * Explicit padding is needed for VPRs, because they use hardware stacking on part of arch_esf and
+ * ESF_SW_IRQ_SIZEOF needs to be calculated accordingly.
+ */
+#define ESF_CSF                                                                                    \
+	_callee_saved_t *csf;                                                                      \
+	unsigned long padding1;                                                                    \
+	unsigned long padding2;                                                                    \
+	unsigned long padding3;
 #else
 #define ESF_CSF
 #endif /* CONFIG_EXCEPTION_DEBUG */
@@ -90,10 +98,13 @@
 
 /*
  * Size of the SW managed part of the ESF in case of interrupt
- *   sizeof(__padding) + ... + sizeof(soc_context)
+ * sizeof(s0) + sizeof(mstatus) + sizeof(soc_context) +...+ sizeof(ESF_CSF)
  */
-#define ESF_SW_IRQ_SIZEOF (0x10)
-
+#ifdef CONFIG_EXCEPTION_DEBUG
+#define ESF_SW_IRQ_SIZEOF      (0x20)
+#else
+#define ESF_SW_IRQ_SIZEOF      (0x10)
+#endif
 /*
  * VPR needs aligned(8) SP when doing HW stacking, if this condition is not fulfilled it will move
  * SP by additional 4 bytes when HW stacking is done. This will be indicated by LSB bit in stacked