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kito-chengstephanosio
kito-cheng
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RISC-V: Add cr and cf constraint
gcc/ChangeLog: * config/riscv/constraints.md (cr): New. (cf): New. * config/riscv/riscv.h (reg_class): Add RVC_GR_REGS and RVC_FP_REGS. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Ditto. * doc/md.texi: Document cr and cf constraint. * config/riscv/riscv.cc (riscv_regno_to_class): Update FP_REGS to RVC_FP_REGS since it smaller set. (riscv_secondary_memory_needed): Handle RVC_FP_REGS. (riscv_register_move_cost): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/constraint-cf-zfinx.c: New. * gcc.target/riscv/constraint-cf.c: New. * gcc.target/riscv/constraint-cr.c: New. (cherry picked from commit 4688857)
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‎gcc/config/riscv/constraints.md‎

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@@ -33,6 +33,12 @@
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(define_register_constraint "l" "JALR_REGS"
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"@internal")
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(define_register_constraint "cr" "RVC_GR_REGS"
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"RVC general purpose register (x8-x15).")
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(define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : (TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
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"RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use zfinx.")
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;; General constraints
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(define_constraint "I"

‎gcc/config/riscv/riscv.cc‎

Lines changed: 17 additions & 11 deletions
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@@ -333,14 +333,14 @@ const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
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JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS,
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JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS,
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SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS,
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RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS,
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RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS,
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RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS,
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RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS,
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RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS,
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RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS,
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RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS, RVC_FP_REGS,
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FRAME_REGS, FRAME_REGS, NO_REGS, NO_REGS,
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NO_REGS, NO_REGS, NO_REGS, NO_REGS,
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NO_REGS, NO_REGS, NO_REGS, NO_REGS,
@@ -8425,9 +8425,11 @@ static bool
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riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1,
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reg_class_t class2)
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{
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bool class1_is_fpr = class1 == FP_REGS || class1 == RVC_FP_REGS;
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bool class2_is_fpr = class2 == FP_REGS || class2 == RVC_FP_REGS;
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return (!riscv_v_ext_mode_p (mode)
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&& GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD
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&& (class1 == FP_REGS) != (class2 == FP_REGS)
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&& (class1_is_fpr != class2_is_fpr)
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&& !TARGET_XTHEADFMV
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&& !TARGET_ZFA);
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}
@@ -8438,8 +8440,12 @@ static int
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riscv_register_move_cost (machine_mode mode,
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reg_class_t from, reg_class_t to)
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{
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if ((from == FP_REGS && to == GR_REGS) ||
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(from == GR_REGS && to == FP_REGS))
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bool from_is_fpr = from == FP_REGS || from == RVC_FP_REGS;
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bool from_is_gpr = from == GR_REGS || from == RVC_GR_REGS;
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bool to_is_fpr = to == FP_REGS || to == RVC_FP_REGS;
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bool to_is_gpr = to == GR_REGS || to == RVC_GR_REGS;
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if ((from_is_fpr && to == to_is_gpr) ||
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(from_is_gpr && to_is_fpr))
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return tune_param->fmv_cost;
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return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2;

‎gcc/config/riscv/riscv.h‎

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@@ -508,8 +508,10 @@ enum reg_class
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{
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NO_REGS, /* no registers in set */
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SIBCALL_REGS, /* registers used by indirect sibcalls */
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RVC_GR_REGS, /* RVC general registers */
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JALR_REGS, /* registers used by indirect calls */
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GR_REGS, /* integer registers */
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RVC_FP_REGS, /* RVC floating-point registers */
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FP_REGS, /* floating-point registers */
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FRAME_REGS, /* arg pointer and frame pointer */
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VM_REGS, /* v0.t registers */
@@ -531,8 +533,10 @@ enum reg_class
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{ \
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"NO_REGS", \
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"SIBCALL_REGS", \
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"RVC_GR_REGS", \
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"JALR_REGS", \
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"GR_REGS", \
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"RVC_FP_REGS", \
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"FP_REGS", \
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"FRAME_REGS", \
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"VM_REGS", \
@@ -556,8 +560,10 @@ enum reg_class
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{ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
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{ 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
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{ 0x0000ff00, 0x00000000, 0x00000000, 0x00000000 }, /* RVC_GR_REGS */ \
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{ 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 }, /* JALR_REGS */ \
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{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
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{ 0x00000000, 0x0000ff00, 0x00000000, 0x00000000 }, /* RVC_FP_REGS */ \
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{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \

‎gcc/doc/md.texi‎

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@@ -3721,6 +3721,13 @@ A vector register, excluding v0 (if available).
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@item vm
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A vector register, only v0 (if available).
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@item cr
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RVC general purpose register (x8-x15).
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@item cf
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RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
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zfinx.
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@end table
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@item RX---@file{config/rx/constraints.md}

‎gcc/testsuite/gcc.target/riscv/constraint-cf-zfinx.c‎

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@@ -0,0 +1,14 @@
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/* { dg-do compile } */
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/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
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/* { dg-options "-march=rv64i_zfinx -mabi=lp64" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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void foo(float a0, float a1, float a2, float a3, float a4, float a5, float a6, float a7, float m0, float m1) {
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/*
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** foo:
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** ...
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** fadd.s\s*t0,\s*(a[0-5]|s[0-1]),\s*(a[0-5]|s[0-1])
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** ...
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*/
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__asm__ volatile("fadd.s t0, %0, %0" : : "cf" (m0));
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}

‎gcc/testsuite/gcc.target/riscv/constraint-cf.c‎

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@@ -0,0 +1,14 @@
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/* { dg-do compile } */
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/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
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/* { dg-options "-march=rv64if -mabi=lp64" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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void foo(float a0, float a1, float a2, float a3, float a4, float a5, float a6, float a7, float m0, float m1) {
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/*
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** foo:
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** ...
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** fadd.s\s*ft0,\s*f(a[0-5]|s[0-1]),\s*f(a[0-5]|s[0-1])
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** ...
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*/
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__asm__ volatile("fadd.s ft0, %0, %0" : : "cf" (m0));
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}

‎gcc/testsuite/gcc.target/riscv/constraint-cr.c‎

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@@ -0,0 +1,13 @@
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/* { dg-do compile } */
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/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
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/* { dg-final { check-function-bodies "**" "" } } */
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void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int m0, int m1) {
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/*
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** foo:
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** ...
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** addi\s*t0,\s*(a[0-5]|s[0-1]),\s*(a[0-5]|s[0-1])
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** ...
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*/
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__asm__ volatile("addi t0, %0, %0" : : "cr" (m0) : "memory");
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}

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