@@ -472,8 +472,11 @@ namespace xsimd
472472
473473 static batch_type abs (const batch_type& rhs)
474474 {
475- return (__m512)(_mm512_and_epi32 ((__m512i)((__m512)(rhs)),
476- _mm512_set1_epi32 (0x7fffffff )));
475+ __m512 rhs_asf = (__m512)rhs;
476+ __m512i rhs_asi = *reinterpret_cast <__m512i*>(&rhs_asf);
477+ __m512i res_asi = _mm512_and_epi32 (_mm512_set1_epi32 (0x7FFFFFFF ),
478+ rhs_asi);
479+ return *reinterpret_cast <__m512*>(&res_asi);
477480 }
478481
479482 static batch_type fabs (const batch_type& rhs)
@@ -510,7 +513,7 @@ namespace xsimd
510513 {
511514 __m256 tmp1 = _mm512_extractf32x8_ps (rhs, 1 );
512515 __m256 tmp2 = _mm512_extractf32x8_ps (rhs, 0 );
513- __m256 res1 = tmp1 + tmp2;
516+ __m256 res1 = _mm256_add_ps ( tmp1, tmp2) ;
514517 return xsimd::hadd (batch<float , 8 >(res1));
515518 }
516519
@@ -524,7 +527,7 @@ namespace xsimd
524527 { \
525528 auto tmp1 = _mm512_shuffle_f32x4 (a, b, _MM_SHUFFLE (1 , 0 , 1 , 0 )); \
526529 auto tmp2 = _mm512_shuffle_f32x4 (a, b, _MM_SHUFFLE (3 , 2 , 3 , 2 )); \
527- res ## I = tmp1 + tmp2; \
530+ res ## I = _mm512_add_ps ( tmp1, tmp2); \
528531 } \
529532
530533 XSIMD_AVX512_HADDP_STEP1 (0 , row[0 ], row[2 ]);
@@ -548,17 +551,17 @@ namespace xsimd
548551 batch<float , 16 > tmp1 = _mm512_shuffle_f32x4 (a, b, _MM_SHUFFLE (2 , 0 , 2 , 0 )); \
549552 batch<float , 16 > tmp2 = _mm512_shuffle_f32x4 (a, b, _MM_SHUFFLE (3 , 1 , 3 , 1 )); \
550553 \
551- batch<float , 16 > resx1 = tmp1 + tmp2; \
554+ batch<float , 16 > resx1 = _mm512_add_ps ( tmp1, tmp2) ; \
552555 \
553556 batch<float , 16 > tmp3 = _mm512_shuffle_f32x4 (c, d, _MM_SHUFFLE (2 , 0 , 2 , 0 )); \
554557 batch<float , 16 > tmp4 = _mm512_shuffle_f32x4 (c, d, _MM_SHUFFLE (3 , 1 , 3 , 1 )); \
555558 \
556- batch<float , 16 > resx2 = tmp3 + tmp4; \
559+ batch<float , 16 > resx2 = _mm512_add_ps ( tmp3, tmp4) ; \
557560 \
558561 batch<float , 16 > tmp5 = _mm512_shuffle_ps (resx1, resx2, _MM_SHUFFLE (2 , 0 , 2 , 0 )); \
559562 batch<float , 16 > tmp6 = _mm512_shuffle_ps (resx1, resx2, _MM_SHUFFLE (3 , 1 , 3 , 1 )); \
560563 \
561- batch<float , 16 > resx3 = tmp5 + tmp6; \
564+ batch<float , 16 > resx3 = _mm512_add_ps ( tmp5, tmp6) ; \
562565 \
563566 halfx ## I = _mm256_hadd_ps (_mm512_extractf32x8_ps (resx3, 0 ), \
564567 _mm512_extractf32x8_ps (resx3, 1 )); \
@@ -576,7 +579,20 @@ namespace xsimd
576579
577580 static batch_type select (const batch_bool_type& cond, const batch_type& a, const batch_type& b)
578581 {
582+ #if !defined(_MSC_VER)
579583 return _mm512_mask_blend_ps (cond, b, a);
584+ #else
585+ __m512i mcondi = _mm512_maskz_broadcastd_epi32 ((__mmask16)cond, _mm_set1_epi32 (~0 ));
586+ __m512 mcond = *reinterpret_cast <__m512*>(&mcondi);
587+ XSIMD_SPLITPS_AVX512 (mcond);
588+ XSIMD_SPLITPS_AVX512 (a);
589+ XSIMD_SPLITPS_AVX512 (b);
590+
591+ auto res_lo = _mm256_blendv_ps (b_low, a_low, mcond_low);
592+ auto res_hi = _mm256_blendv_ps (b_high, a_high, mcond_high);
593+
594+ XSIMD_RETURN_MERGEDPS_AVX (res_lo, res_hi);
595+ #endif
580596 }
581597
582598 static batch_bool_type isnan (const batch_type& x)
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