@@ -95,8 +95,10 @@ namespace xsimd
9595 } \
9696 template <> \
9797 XSIMD_INLINE type bitcast<type>(type x) noexcept { return x; } \
98- static XSIMD_INLINE byte_type as_bytes (type x) noexcept \
98+ template <class U > \
99+ static XSIMD_INLINE byte_type as_bytes (U x) noexcept \
99100 { \
101+ static_assert (std::is_same<U, type>::value, " inconsistent conversion types" ); \
100102 const auto words = XSIMD_RVV_JOINT5 (__riscv_vreinterpret_, u, s, m, vmul)(x); \
101103 return XSIMD_RVV_JOINT5 (__riscv_vreinterpret_, u, 8 , m, vmul)(words); \
102104 } \
@@ -133,6 +135,74 @@ namespace xsimd
133135 {
134136 return __riscv_vreinterpret_i8m8 (x);
135137 }
138+ template <>
139+ XSIMD_INLINE rvv_type_info<int8_t , rvv_width_m1 * 1 >::type
140+ rvv_type_info<int8_t , rvv_width_m1 * 1 >::bitcast<__rvv_uint8m1_t >(
141+ __rvv_uint8m1_t x) noexcept
142+ {
143+ return __riscv_vreinterpret_i8m1 (x);
144+ }
145+ template <>
146+ XSIMD_INLINE rvv_type_info<uint16_t , rvv_width_m1 * 1 >::type
147+ rvv_type_info<uint16_t , rvv_width_m1 * 1 >::bitcast<__rvv_uint8m1_t >(
148+ __rvv_uint8m1_t x) noexcept
149+ {
150+ return __riscv_vreinterpret_u16m1 (x);
151+ }
152+ template <>
153+ XSIMD_INLINE rvv_type_info<uint32_t , rvv_width_m1 * 1 >::type
154+ rvv_type_info<uint32_t , rvv_width_m1 * 1 >::bitcast<__rvv_uint8m1_t >(
155+ __rvv_uint8m1_t x) noexcept
156+ {
157+ return __riscv_vreinterpret_u32m1 (x);
158+ }
159+ template <>
160+ XSIMD_INLINE rvv_type_info<uint64_t , rvv_width_m1 * 1 >::type
161+ rvv_type_info<uint64_t , rvv_width_m1 * 1 >::bitcast<__rvv_uint8m1_t >(
162+ __rvv_uint8m1_t x) noexcept
163+ {
164+ return __riscv_vreinterpret_u64m1 (x);
165+ }
166+
167+ //
168+
169+ template <>
170+ XSIMD_INLINE rvv_type_info<int8_t , rvv_width_m1 * 8 >::byte_type
171+ rvv_type_info<int8_t , rvv_width_m1 * 8 >::as_bytes<__rvv_int8m8_t >(__rvv_int8m8_t x) noexcept
172+ {
173+ return __riscv_vreinterpret_u8m8 (x);
174+ }
175+ template <>
176+ XSIMD_INLINE rvv_type_info<int8_t , rvv_width_m1 * 1 >::byte_type
177+ rvv_type_info<int8_t , rvv_width_m1 * 1 >::as_bytes<__rvv_int8m1_t >(__rvv_int8m1_t x) noexcept
178+ {
179+ return __riscv_vreinterpret_u8m1 (x);
180+ }
181+
182+ template <>
183+ XSIMD_INLINE rvv_type_info<uint8_t , rvv_width_m1 * 1 >::byte_type
184+ rvv_type_info<uint8_t , rvv_width_m1 * 1 >::as_bytes<__rvv_uint8m1_t >(__rvv_uint8m1_t x) noexcept
185+ {
186+ return x;
187+ }
188+ template <>
189+ XSIMD_INLINE rvv_type_info<uint16_t , rvv_width_m1 * 1 >::byte_type
190+ rvv_type_info<uint16_t , rvv_width_m1 * 1 >::as_bytes<__rvv_uint16m1_t >(__rvv_uint16m1_t x) noexcept
191+ {
192+ return __riscv_vreinterpret_u8m1 (x);
193+ }
194+ template <>
195+ XSIMD_INLINE rvv_type_info<uint32_t , rvv_width_m1 * 1 >::byte_type
196+ rvv_type_info<uint32_t , rvv_width_m1 * 1 >::as_bytes<__rvv_uint32m1_t >(__rvv_uint32m1_t x) noexcept
197+ {
198+ return __riscv_vreinterpret_u8m1 (x);
199+ }
200+ template <>
201+ XSIMD_INLINE rvv_type_info<uint64_t , rvv_width_m1 * 1 >::byte_type
202+ rvv_type_info<uint64_t , rvv_width_m1 * 1 >::as_bytes<__rvv_uint64m1_t >(__rvv_uint64m1_t x) noexcept
203+ {
204+ return __riscv_vreinterpret_u8m1 (x);
205+ }
136206
137207 // rvv_blob is storage-type abstraction for a vector register.
138208 template <class T , size_t Width>
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