Provide an MSVC compatible usage of various mask-related intrinsics

Downgrade to AVX2 when MSVC doesn't support the AVX512 builtin.

This could be improved based on the compiler version, better safe than sorry
here.

Author: serge-sans-paille

include/xsimd/types/xsimd_avx512_float.hpp

@@ -579,7 +579,20 @@ namespace xsimd
 
             static batch_type select(const batch_bool_type& cond, const batch_type& a, const batch_type& b)
             {
+            #if !defined(_MSC_VER)
                 return _mm512_mask_blend_ps(cond, b, a);
+            #else
+                __m512i mcondi = _mm512_maskz_broadcastd_epi32 ((__mmask16)cond, _mm_set1_epi32(~0));
+                __m512 mcond = *reinterpret_cast<__m512*>(&mcondi);
+                XSIMD_SPLITPS_AVX512(mcond);
+                XSIMD_SPLITPS_AVX512(a);
+                XSIMD_SPLITPS_AVX512(b);
+
+                auto res_lo = _mm256_blendv_ps(b_low, a_low, mcond_low);
+                auto res_hi = _mm256_blendv_ps(b_high, a_high, mcond_high);
+
+                XSIMD_RETURN_MERGEDPS_AVX(res_lo, res_hi);
+            #endif
             }
 
             static batch_bool_type isnan(const batch_type& x)

include/xsimd/types/xsimd_avx512_int16.hpp

@@ -316,19 +316,17 @@ namespace xsimd
 
             static batch_type select(const batch_bool_type& cond, const batch_type& a, const batch_type& b)
             {
-            #if defined(XSIMD_AVX512BW_AVAILABLE)
-                // Some compilers are not happy with passing directly a and b to the intrinsics
-                // See https://github.com/xtensor-stack/xsimd/issues/315
-                __m512i ma = a;
-                __m512i mb = b;
-                return _mm512_mask_blend_epi16(cond, mb, ma);
+            #if defined(XSIMD_AVX512BW_AVAILABLE) && !defined(_MSC_VER)
+                auto res = _mm512_mask_blend_epi16((__mmask32)cond, (__m512i)b, (__m512i)a);
+                return batch_type(res);
             #else
-                XSIMD_SPLIT_AVX512(cond);
+                __m512i mcond = _mm512_maskz_broadcastw_epi16((__mmask32)cond, _mm_set1_epi32(~0));
+                XSIMD_SPLIT_AVX512(mcond);
                 XSIMD_SPLIT_AVX512(a);
                 XSIMD_SPLIT_AVX512(b);
 
-                auto res_lo = _mm256_blendv_epi8(b_low, a_low, cond_low);
-                auto res_hi = _mm256_blendv_epi8(b_high, a_high, cond_high);
+                auto res_lo = _mm256_blendv_epi8(b_low, a_low, mcond_low);
+                auto res_hi = _mm256_blendv_epi8(b_high, a_high, mcond_high);
 
                 XSIMD_RETURN_MERGED_AVX(res_lo, res_hi);
             #endif

include/xsimd/types/xsimd_avx512_int64.hpp

@@ -299,7 +299,19 @@ namespace xsimd
 
             static batch_type select(const batch_bool_type& cond, const batch_type& a, const batch_type& b)
             {
+            #if !defined(_MSC_VER)
                 return _mm512_mask_blend_epi64(cond, b, a);
+            #else
+                __m512i mcond = _mm512_maskz_broadcastq_epi64((__mmask8)cond, _mm_set1_epi32(~0));
+                XSIMD_SPLIT_AVX512(mcond);
+                XSIMD_SPLIT_AVX512(a);
+                XSIMD_SPLIT_AVX512(b);
+
+                auto res_lo = _mm256_blendv_epi8(b_low, a_low, mcond_low);
+                auto res_hi = _mm256_blendv_epi8(b_high, a_high, mcond_high);
+
+                XSIMD_RETURN_MERGED_AVX(res_lo, res_hi);
+            #endif
             }
         };
 

include/xsimd/types/xsimd_avx512_int_base.hpp

@@ -18,13 +18,29 @@ namespace xsimd
 {
 
 #define XSIMD_SPLIT_AVX512(avx_name)                                                                  \
-    __m256i avx_name##_low = _mm512_castsi512_si256(avx_name);                                        \
-    __m256i avx_name##_high = _mm512_extracti64x4_epi64(avx_name, 1)                                  \
+    __m256i avx_name##_low = _mm512_castsi512_si256((__m512i)avx_name);                                        \
+    __m256i avx_name##_high = _mm512_extracti64x4_epi64((__m512i)avx_name, 1)                                  \
+
+#define XSIMD_SPLITPS_AVX512(avx_name)                                                                  \
+    __m256 avx_name##_low = _mm512_castps512_ps256((__m512)avx_name);                                        \
+    __m256 avx_name##_high = _mm512_extractf32x8_ps((__m512)avx_name, 1)                                  \
+
+#define XSIMD_SPLITPD_AVX512(avx_name)                                                                  \
+    __m256d avx_name##_low = _mm512_castpd512_pd256((__m512d)avx_name);                                        \
+    __m256d avx_name##_high = _mm512_extractf64x4_pd((__m512d)avx_name, 1)                                  \
 
 #define XSIMD_RETURN_MERGED_AVX(res_low, res_high)                                                    \
     __m512i result = _mm512_castsi256_si512(res_low);                                                 \
     return _mm512_inserti64x4(result, res_high, 1)                                                    \
 
+#define XSIMD_RETURN_MERGEDPS_AVX(res_low, res_high)                                                    \
+    __m512 result = _mm512_castps256_ps512(res_low);                                                 \
+    return _mm512_insertf32x8(result, res_high, 1)                                                    \
+
+#define XSIMD_RETURN_MERGEDPD_AVX(res_low, res_high)                                                    \
+    __m512d result = _mm512_castpd256_pd512(res_low);                                                 \
+    return _mm512_insertf64x4(result, res_high, 1)                                                    \
+
 #define XSIMD_APPLY_AVX2_FUNCTION(N, func, avx_lhs, avx_rhs)                                          \
     XSIMD_SPLIT_AVX512(avx_lhs);                                                                      \
     XSIMD_SPLIT_AVX512(avx_rhs);                                                                      \