WIP

serge-sans-paille · serge-sans-paille · commit 6bad43f384a1 · 2025-01-15T22:35:42.000+01:00
diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -147,21 +147,21 @@ namespace xsimd
             rvv_type_info<int16_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
                 __rvv_uint8m1_t x) noexcept
             {
-                return __riscv_vreinterpret_i16m1(x);
+                return __riscv_vreinterpret_i16m1(__riscv_vreinterpret_u16m1(x));
             }
             template <>
             XSIMD_INLINE rvv_type_info<int32_t, rvv_width_m1 * 1>::type
             rvv_type_info<int32_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
                 __rvv_uint8m1_t x) noexcept
             {
-                return __riscv_vreinterpret_i32m1(x);
+                return __riscv_vreinterpret_i32m1(__riscv_vreinterpret_u32m1(x));
             }
             template <>
             XSIMD_INLINE rvv_type_info<int64_t, rvv_width_m1 * 1>::type
             rvv_type_info<int64_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
                 __rvv_uint8m1_t x) noexcept
             {
-                return __riscv_vreinterpret_i64m1(x);
+                return __riscv_vreinterpret_i64m1(__riscv_vreinterpret_u64m1(x));
             }
             template <>
             XSIMD_INLINE rvv_type_info<uint16_t, rvv_width_m1 * 1>::type

Original file line number	Diff line number	Diff line change
`@@ -147,21 +147,21 @@ namespace xsimd`
`147`	`147`	`rvv_type_info<int16_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(`
`148`	`148`	`__rvv_uint8m1_t x) noexcept`
`149`	`149`	`{`
`150`		`- return __riscv_vreinterpret_i16m1(x);`
	`150`	`+ return __riscv_vreinterpret_i16m1(__riscv_vreinterpret_u16m1(x));`
`151`	`151`	`}`
`152`	`152`	`template <>`
`153`	`153`	`XSIMD_INLINE rvv_type_info<int32_t, rvv_width_m1 * 1>::type`
`154`	`154`	`rvv_type_info<int32_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(`
`155`	`155`	`__rvv_uint8m1_t x) noexcept`
`156`	`156`	`{`
`157`		`- return __riscv_vreinterpret_i32m1(x);`
	`157`	`+ return __riscv_vreinterpret_i32m1(__riscv_vreinterpret_u32m1(x));`
`158`	`158`	`}`
`159`	`159`	`template <>`
`160`	`160`	`XSIMD_INLINE rvv_type_info<int64_t, rvv_width_m1 * 1>::type`
`161`	`161`	`rvv_type_info<int64_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(`
`162`	`162`	`__rvv_uint8m1_t x) noexcept`
`163`	`163`	`{`
`164`		`- return __riscv_vreinterpret_i64m1(x);`
	`164`	`+ return __riscv_vreinterpret_i64m1(__riscv_vreinterpret_u64m1(x));`
`165`	`165`	`}`
`166`	`166`	`template <>`
`167`	`167`	`XSIMD_INLINE rvv_type_info<uint16_t, rvv_width_m1 * 1>::type`