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1 parent 1123841 commit c3382a3Copy full SHA for c3382a3
vpython/rate_control.py
@@ -66,7 +66,6 @@ def _sleep(dt):
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return
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tend = _clock()+dt
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while _clock() < tend:
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- print (tend- _clock(),tend)
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pass
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class simulateDelay:
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