We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
2 parents 9e6782f + 861b55b commit 139924aCopy full SHA for 139924a
vpython/cyvector.pyx
@@ -1,3 +1,5 @@
1
+# cython: language_level=3
2
+
3
from random import random
4
5
# List of names imported from this module with import *
vpython/rate_control.py
@@ -66,7 +66,6 @@ def _sleep(dt):
66
return
67
tend = _clock()+dt
68
while _clock() < tend:
69
- print (tend- _clock(),tend)
70
pass
71
72
class simulateDelay:
0 commit comments