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1 | 1 | //! Inter-IC Sound (I2S) |
| 2 | +use core::sync::atomic::{fence, Ordering}; |
| 3 | + |
2 | 4 | use embassy_hal_internal::into_ref; |
3 | 5 |
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4 | 6 | use crate::dma::{ringbuffer, word, Channel, NoDma, TransferOptions, WritableRingBuffer}; |
@@ -264,6 +266,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> I2S<'d, T, C, W> { |
264 | 266 |
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265 | 267 | let opts = TransferOptions { |
266 | 268 | half_transfer_ir: true, |
| 269 | + |
267 | 270 | //the new_write() and new_read() always use circular mode |
268 | 271 | ..Default::default() |
269 | 272 | }; |
@@ -312,19 +315,17 @@ impl<'d, T: Instance, C: Channel, W: word::Word> I2S<'d, T, C, W> { |
312 | 315 | // spi_cfg.frequency = freq; |
313 | 316 | // let spi = Spi::new_internal(peri, NoDma, NoDma, spi_cfg); |
314 | 317 |
|
315 | | - |
316 | | - // TODO move i2s to the new mux infra. |
317 | | - //#[cfg(all(rcc_f4, not(stm32f410)))] |
318 | | - //let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap(); |
319 | | - //#[cfg(stm32f410)] |
320 | | - let pclk = T::frequency(); |
| 318 | + // TODO move i2s to the new mux infra. |
| 319 | + //#[cfg(all(rcc_f4, not(stm32f410)))] |
| 320 | + //let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap(); |
| 321 | + //#[cfg(stm32f410)] |
| 322 | + // let pclk = T::frequency(); |
321 | 323 | // #[cfg(all(rcc_f4, not(stm32f410)))] |
322 | 324 | // let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap(); |
323 | 325 |
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324 | 326 | // #[cfg(stm32f410)] |
325 | 327 | // let pclk = T::frequency(); |
326 | 328 |
|
327 | | - |
328 | 329 | // let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format); |
329 | 330 |
|
330 | 331 | // #[cfg(any(spi_v1, spi_f1))] |
@@ -421,6 +422,12 @@ impl<'d, T: Instance, C: Channel, W: word::Word> I2S<'d, T, C, W> { |
421 | 422 | }); |
422 | 423 |
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423 | 424 | self.ring_buffer.request_stop(); |
| 425 | + while self.ring_buffer.is_running() {} |
| 426 | + |
| 427 | + // "Subsequent reads and writes cannot be moved ahead of preceding reads." |
| 428 | + fence(Ordering::SeqCst); |
| 429 | + |
| 430 | + // self.ring_buffer.clear(); |
424 | 431 |
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425 | 432 | T::REGS.cr1().modify(|w| { |
426 | 433 | w.set_spe(false); |
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