Merge pull request #12 from twilco/post-four

Post four

Author: twilco

_posts/2019-04-27-riscv-from-scratch-2.markdown

@@ -31,7 +31,6 @@ git clone git@github.com:twilco/riscv-from-scratch.git
 # via HTTPS rather than SSH
 # alternatively, if you are a GitHub user, you can fork this repo.
 # https://help.github.com/en/articles/fork-a-repo
-
 cd riscv-from-scratch/work
 {% endhighlight %}
 
@@ -530,9 +529,11 @@ From here we can use `gdb` as normal - `s` to step to the next instruction, `inf
 
 ### What's next
 
-We accomplished, and hopefully learned, a lot today!  I've never had a formal plan for this series, instead simply following whatever is most interesting to me at each moment, so I'm not sure exactly sure what will come next.  I particularly enjoyed the deep dive we took into the `jal` instruction, so perhaps in our next post we'll build upon the foundation we created here but instead replace `add.c` with some pure RISC-V assembly program.  If you have something in particular you'd like to see or have any questions about what we covered here, let me know by opening an issue at [https://github.com/twilco/twilco.github.io/issues](https://github.com/twilco/twilco.github.io/issues).  After the next post in the series is complete I'll link to it below.
+In our next post, we'll continue to build on our knowledge of RISC-V assembly by beginning implementation of a driver for the UART onboard the `virt` QEMU machine.  Expect to learn about what a UART is and how it works, additional devicetree properties, the basic building blocks required to implement an NS16550A-compatible UART driver, and more.
+
+Sound interesting?  This post has been released - [click here to check it out](https://twilco.github.io{% post_url 2019-07-08-riscv-from-scratch-3 %}).  If you have any questions, comments, or corrections, feel free to [open up an issue](https://github.com/twilco/twilco.github.io/issues) or leave a comment below via [utterances](https://github.com/utterance/utterances).
 
-Thanks for reading, and hope to see you in the next post!
+Thanks for reading!
 
 ### Extra credit
 

_posts/2019-07-08-riscv-from-scratch-3.markdown

@@ -28,8 +28,8 @@ So, without further ado, let's begin.
 UART stands for "**U**niversal **A**synchronous **R**eceiver-**T**ransmitter", and is a physical hardware device (_not_ a protocol, à la [I2C](https://en.wikipedia.org/wiki/I%C2%B2C) or [SPI](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface)) used to transmit and receive serial data.  Serial data transmission is the process of sending data sequentially, bit-by-bit.  In contrast, parallel data transmission is the process of sending multiple bits all at once.  This image from the [serial communication Wikipedia page](https://en.wikipedia.org/wiki/Serial_communication) illustrates the difference well:
 
 {:refdef: style="text-align: center;"}
-<a href="/assets/img/riscv-from-scratch-pt-3/Parallel_and_Serial_Transmission.gif">![serial and parallel transmission contrasted](/assets/img/riscv-from-scratch-pt-3/Parallel_and_Serial_Transmission.gif)</a>
-{: refdef}
+<a href="/assets/img/riscv-from-scratch/pt-3/Parallel_and_Serial_Transmission.gif">![serial and parallel transmission contrasted](/assets/img/riscv-from-scratch/pt-3/Parallel_and_Serial_Transmission.gif)</a>
+{:refdef}
 
 UARTs never specify a rate at which data should be received or transmitted (also called a *clock rate* or *clock signal*), which is what makes them asynchronous rather than synchronous.  Instead, transmitting UARTs frame each packet of data with start and stop bits, which informs receiving UARTs of when to start and stop reading data.
 
@@ -266,6 +266,7 @@ Today we learned about UARTs and USARTs, the NS16550A specification, interrupts,
 
 In the next post, we'll discuss and implement _function prologues_ for our two driver functions `uart_get_char` and `uart_put_char`.  Function prologues are an important part of making function calls possible in the world of assembly.  We will be walking through a function prologue step-by-step, with diagrams detailing changes to the stack and registers with every instruction.
 
-When the next post is complete I'll link it here.  If you have any questions, comments, or corrections, feel free to [open up an issue](https://github.com/twilco/twilco.github.io/issues) or leave a comment below via [utterances](https://github.com/utterance/utterances).
+This post has been released - [click here to check it out]({% post_url 2019-07-28-riscv-from-scratch-4 %}).  If you have any questions, comments, or corrections, feel free to [open up an issue](https://github.com/twilco/twilco.github.io/issues) or leave a comment below via [utterances](https://github.com/utterance/utterances).
+
+Thanks for reading!
 
-Thanks for reading - hope to see you in the next post!