Simple agent-based model simulation.
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Sep 4, 2016 - JavaScript
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model-simulation
Here are 10 public repositories matching this topic...
All the necessary code and instructions to analyse datasets and model simulations for higher-order Heaps' laws.
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Oct 24, 2023 - Jupyter Notebook
Open-source implementation of the Foundational Semantics for Executable UML Models (fUML) and Precise Semantics of UML Composite Structures (PSCS) specifications for C++.
cpp uml code-generation model-driven-development model-simulation model-driven-engineering fuml pscs executable-uml model-driven-software-engineering model-execution
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Jul 9, 2024 - C++
Simulaciones de Sistemas usando python con Qt
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Feb 24, 2017 - Python
Open-source implementation of the Foundational Semantics for Executable UML Models (fUML) and Precise Semantics of UML Composite Structures (PSCS) specifications for Java.
java uml code-generation model-driven-development model-simulation model-driven-engineering fuml pscs executable-uml model-driven-software-engineering model-execution
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Feb 4, 2025 - Java
ARM architecture single-cycle processor designed according to book "Digital design and computer architecture: ARM edition" as a practice in digital design.
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Jun 27, 2019 - SystemVerilog
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Jul 31, 2024 - Jupyter Notebook
Julia and MATLAB coursework at the Stockholm School of Economics and Stockholm University
matlab julia-language dynamic-programming model-simulation computational-economics value-function-iteration welfare-analysis
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Dec 4, 2024 - Jupyter Notebook
Open-source implementation of the Foundational Semantics for Executable UML Models (fUML) and Precise Semantics of UML Composite Structures (PSCS) specifications for C#.
csharp uml code-generation model-driven-development model-simulation model-driven-engineering fuml pscs executable-uml model-driven-software-engineering model-execution
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Oct 24, 2024 - C#
🎛️ Convert Verilog code to C for efficient simulation and synthesis, streamlining design workflows and enhancing hardware development processes.
open-source fpga simulation verilog model-simulation testbench digital-design hardware-description-language circuit-design electronic-design-automation design-verification rtl-design c2w synthesizable-verilog synthesis-tools
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Nov 12, 2025
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