Skip to content

Commit dafff71

Browse files
avencanavencan
authored
Added support for the Aventen S3 Sync (espressif#8587)
* Added support for the Aventen S3 Sync * Update pins_arduino.h
1 parent 8bfe3c4 commit dafff71

File tree

2 files changed

+287
-0
lines changed

2 files changed

+287
-0
lines changed

‎boards.txt‎

Lines changed: 216 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1767,6 +1767,222 @@ esp32wroverkit.menu.EraseFlash.all.upload.erase_cmd=-e
17671767

17681768
##############################################################
17691769

1770+
aventen_s3_sync.name=Aventen S3 Sync
1771+
aventen_s3_sync.vid.0=0x303a
1772+
aventen_s3_sync.pid.0=0x1001
1773+
## Based upon ESP32-S3 Dev Board
1774+
1775+
aventen_s3_sync.bootloader.tool=esptool_py
1776+
aventen_s3_sync.bootloader.tool.default=esptool_py
1777+
1778+
aventen_s3_sync.upload.tool=esptool_py
1779+
aventen_s3_sync.upload.tool.default=esptool_py
1780+
aventen_s3_sync.upload.tool.network=esp_ota
1781+
1782+
aventen_s3_sync.upload.maximum_size=1310720
1783+
aventen_s3_sync.upload.maximum_data_size=327680
1784+
aventen_s3_sync.upload.flags=
1785+
aventen_s3_sync.upload.extra_flags=
1786+
aventen_s3_sync.upload.use_1200bps_touch=false
1787+
aventen_s3_sync.upload.wait_for_upload_port=false
1788+
1789+
aventen_s3_sync.serial.disableDTR=false
1790+
aventen_s3_sync.serial.disableRTS=false
1791+
1792+
aventen_s3_sync.build.tarch=xtensa
1793+
aventen_s3_sync.build.bootloader_addr=0x0
1794+
aventen_s3_sync.build.target=esp32s3
1795+
aventen_s3_sync.build.mcu=esp32s3
1796+
aventen_s3_sync.build.core=esp32
1797+
aventen_s3_sync.build.variant=Aventen_S3_Sync
1798+
aventen_s3_sync.build.board=AVENTEN_S3_SYNC
1799+
1800+
aventen_s3_sync.build.usb_mode=1
1801+
aventen_s3_sync.build.cdc_on_boot=0
1802+
aventen_s3_sync.build.msc_on_boot=0
1803+
aventen_s3_sync.build.dfu_on_boot=0
1804+
aventen_s3_sync.build.f_cpu=240000000L
1805+
aventen_s3_sync.build.flash_size=16MB
1806+
aventen_s3_sync.build.flash_freq=80m
1807+
aventen_s3_sync.build.flash_mode=dio
1808+
aventen_s3_sync.build.boot=qio
1809+
aventen_s3_sync.build.boot_freq=80m
1810+
aventen_s3_sync.build.partitions=default
1811+
aventen_s3_sync.build.defines=
1812+
aventen_s3_sync.build.loop_core=
1813+
aventen_s3_sync.build.event_core=
1814+
aventen_s3_sync.build.psram_type=qspi
1815+
aventen_s3_sync.build.memory_type={build.boot}_{build.psram_type}
1816+
1817+
## IDE 2.0
1818+
aventen_s3_sync.menu.JTAGAdapter.default=Disabled
1819+
aventen_s3_sync.menu.JTAGAdapter.default.build.copy_jtag_files=0
1820+
aventen_s3_sync.menu.JTAGAdapter.builtin=Integrated USB JTAG
1821+
aventen_s3_sync.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
1822+
aventen_s3_sync.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
1823+
aventen_s3_sync.menu.JTAGAdapter.external=FTDI Adapter
1824+
aventen_s3_sync.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
1825+
aventen_s3_sync.menu.JTAGAdapter.external.build.copy_jtag_files=1
1826+
aventen_s3_sync.menu.JTAGAdapter.bridge=ESP USB Bridge
1827+
aventen_s3_sync.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
1828+
aventen_s3_sync.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
1829+
1830+
aventen_s3_sync.menu.PSRAM.disabled=Disabled
1831+
aventen_s3_sync.menu.PSRAM.disabled.build.defines=
1832+
aventen_s3_sync.menu.PSRAM.disabled.build.psram_type=qspi
1833+
aventen_s3_sync.menu.PSRAM.enabled=QSPI PSRAM
1834+
aventen_s3_sync.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
1835+
aventen_s3_sync.menu.PSRAM.enabled.build.psram_type=qspi
1836+
aventen_s3_sync.menu.PSRAM.opi=OPI PSRAM
1837+
aventen_s3_sync.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
1838+
aventen_s3_sync.menu.PSRAM.opi.build.psram_type=opi
1839+
1840+
aventen_s3_sync.menu.FlashMode.qio=QIO 80MHz
1841+
aventen_s3_sync.menu.FlashMode.qio.build.flash_mode=dio
1842+
aventen_s3_sync.menu.FlashMode.qio.build.boot=qio
1843+
aventen_s3_sync.menu.FlashMode.qio.build.boot_freq=80m
1844+
aventen_s3_sync.menu.FlashMode.qio.build.flash_freq=80m
1845+
aventen_s3_sync.menu.FlashMode.qio120=QIO 120MHz
1846+
aventen_s3_sync.menu.FlashMode.qio120.build.flash_mode=dio
1847+
aventen_s3_sync.menu.FlashMode.qio120.build.boot=qio
1848+
aventen_s3_sync.menu.FlashMode.qio120.build.boot_freq=120m
1849+
aventen_s3_sync.menu.FlashMode.qio120.build.flash_freq=80m
1850+
aventen_s3_sync.menu.FlashMode.dio=DIO 80MHz
1851+
aventen_s3_sync.menu.FlashMode.dio.build.flash_mode=dio
1852+
aventen_s3_sync.menu.FlashMode.dio.build.boot=dio
1853+
aventen_s3_sync.menu.FlashMode.dio.build.boot_freq=80m
1854+
aventen_s3_sync.menu.FlashMode.dio.build.flash_freq=80m
1855+
aventen_s3_sync.menu.FlashMode.opi=OPI 80MHz
1856+
aventen_s3_sync.menu.FlashMode.opi.build.flash_mode=dout
1857+
aventen_s3_sync.menu.FlashMode.opi.build.boot=opi
1858+
aventen_s3_sync.menu.FlashMode.opi.build.boot_freq=80m
1859+
aventen_s3_sync.menu.FlashMode.opi.build.flash_freq=80m
1860+
1861+
aventen_s3_sync.menu.FlashSize.16M=16MB (128Mb)
1862+
aventen_s3_sync.menu.FlashSize.16M.build.flash_size=16MB
1863+
1864+
aventen_s3_sync.menu.LoopCore.1=Core 1
1865+
aventen_s3_sync.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
1866+
aventen_s3_sync.menu.LoopCore.0=Core 0
1867+
aventen_s3_sync.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
1868+
1869+
aventen_s3_sync.menu.EventsCore.1=Core 1
1870+
aventen_s3_sync.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
1871+
aventen_s3_sync.menu.EventsCore.0=Core 0
1872+
aventen_s3_sync.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
1873+
1874+
aventen_s3_sync.menu.USBMode.hwcdc=Hardware CDC and JTAG
1875+
aventen_s3_sync.menu.USBMode.hwcdc.build.usb_mode=1
1876+
aventen_s3_sync.menu.USBMode.default=USB-OTG (TinyUSB)
1877+
aventen_s3_sync.menu.USBMode.default.build.usb_mode=0
1878+
1879+
aventen_s3_sync.menu.CDCOnBoot.default=Disabled
1880+
aventen_s3_sync.menu.CDCOnBoot.default.build.cdc_on_boot=0
1881+
aventen_s3_sync.menu.CDCOnBoot.cdc=Enabled
1882+
aventen_s3_sync.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
1883+
1884+
aventen_s3_sync.menu.MSCOnBoot.default=Disabled
1885+
aventen_s3_sync.menu.MSCOnBoot.default.build.msc_on_boot=0
1886+
aventen_s3_sync.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
1887+
aventen_s3_sync.menu.MSCOnBoot.msc.build.msc_on_boot=1
1888+
1889+
aventen_s3_sync.menu.DFUOnBoot.default=Disabled
1890+
aventen_s3_sync.menu.DFUOnBoot.default.build.dfu_on_boot=0
1891+
aventen_s3_sync.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
1892+
aventen_s3_sync.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
1893+
1894+
aventen_s3_sync.menu.UploadMode.default=UART0 / Hardware CDC
1895+
aventen_s3_sync.menu.UploadMode.default.upload.use_1200bps_touch=false
1896+
aventen_s3_sync.menu.UploadMode.default.upload.wait_for_upload_port=false
1897+
aventen_s3_sync.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
1898+
aventen_s3_sync.menu.UploadMode.cdc.upload.use_1200bps_touch=true
1899+
aventen_s3_sync.menu.UploadMode.cdc.upload.wait_for_upload_port=true
1900+
1901+
aventen_s3_sync.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
1902+
aventen_s3_sync.menu.PartitionScheme.default.build.partitions=default
1903+
aventen_s3_sync.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
1904+
aventen_s3_sync.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
1905+
aventen_s3_sync.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
1906+
aventen_s3_sync.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
1907+
aventen_s3_sync.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
1908+
aventen_s3_sync.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
1909+
aventen_s3_sync.menu.PartitionScheme.minimal.build.partitions=minimal
1910+
aventen_s3_sync.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
1911+
aventen_s3_sync.menu.PartitionScheme.no_ota.build.partitions=no_ota
1912+
aventen_s3_sync.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
1913+
aventen_s3_sync.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
1914+
aventen_s3_sync.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
1915+
aventen_s3_sync.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
1916+
aventen_s3_sync.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
1917+
aventen_s3_sync.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
1918+
aventen_s3_sync.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
1919+
aventen_s3_sync.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
1920+
aventen_s3_sync.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
1921+
aventen_s3_sync.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
1922+
aventen_s3_sync.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
1923+
aventen_s3_sync.menu.PartitionScheme.huge_app.build.partitions=huge_app
1924+
aventen_s3_sync.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
1925+
aventen_s3_sync.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
1926+
aventen_s3_sync.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
1927+
aventen_s3_sync.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
1928+
aventen_s3_sync.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
1929+
aventen_s3_sync.menu.PartitionScheme.fatflash.build.partitions=ffat
1930+
aventen_s3_sync.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
1931+
aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
1932+
aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
1933+
aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
1934+
aventen_s3_sync.menu.PartitionScheme.rainmaker=RainMaker
1935+
aventen_s3_sync.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
1936+
aventen_s3_sync.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728
1937+
1938+
aventen_s3_sync.menu.CPUFreq.240=240MHz (WiFi)
1939+
aventen_s3_sync.menu.CPUFreq.240.build.f_cpu=240000000L
1940+
aventen_s3_sync.menu.CPUFreq.160=160MHz (WiFi)
1941+
aventen_s3_sync.menu.CPUFreq.160.build.f_cpu=160000000L
1942+
aventen_s3_sync.menu.CPUFreq.80=80MHz (WiFi)
1943+
aventen_s3_sync.menu.CPUFreq.80.build.f_cpu=80000000L
1944+
aventen_s3_sync.menu.CPUFreq.40=40MHz
1945+
aventen_s3_sync.menu.CPUFreq.40.build.f_cpu=40000000L
1946+
aventen_s3_sync.menu.CPUFreq.20=20MHz
1947+
aventen_s3_sync.menu.CPUFreq.20.build.f_cpu=20000000L
1948+
aventen_s3_sync.menu.CPUFreq.10=10MHz
1949+
aventen_s3_sync.menu.CPUFreq.10.build.f_cpu=10000000L
1950+
1951+
aventen_s3_sync.menu.UploadSpeed.921600=921600
1952+
aventen_s3_sync.menu.UploadSpeed.921600.upload.speed=921600
1953+
aventen_s3_sync.menu.UploadSpeed.115200=115200
1954+
aventen_s3_sync.menu.UploadSpeed.115200.upload.speed=115200
1955+
aventen_s3_sync.menu.UploadSpeed.256000.windows=256000
1956+
aventen_s3_sync.menu.UploadSpeed.256000.upload.speed=256000
1957+
aventen_s3_sync.menu.UploadSpeed.230400.windows.upload.speed=256000
1958+
aventen_s3_sync.menu.UploadSpeed.230400=230400
1959+
aventen_s3_sync.menu.UploadSpeed.230400.upload.speed=230400
1960+
aventen_s3_sync.menu.UploadSpeed.460800.linux=460800
1961+
aventen_s3_sync.menu.UploadSpeed.460800.macosx=460800
1962+
aventen_s3_sync.menu.UploadSpeed.460800.upload.speed=460800
1963+
aventen_s3_sync.menu.UploadSpeed.512000.windows=512000
1964+
aventen_s3_sync.menu.UploadSpeed.512000.upload.speed=512000
1965+
1966+
aventen_s3_sync.menu.DebugLevel.none=None
1967+
aventen_s3_sync.menu.DebugLevel.none.build.code_debug=0
1968+
aventen_s3_sync.menu.DebugLevel.error=Error
1969+
aventen_s3_sync.menu.DebugLevel.error.build.code_debug=1
1970+
aventen_s3_sync.menu.DebugLevel.warn=Warn
1971+
aventen_s3_sync.menu.DebugLevel.warn.build.code_debug=2
1972+
aventen_s3_sync.menu.DebugLevel.info=Info
1973+
aventen_s3_sync.menu.DebugLevel.info.build.code_debug=3
1974+
aventen_s3_sync.menu.DebugLevel.debug=Debug
1975+
aventen_s3_sync.menu.DebugLevel.debug.build.code_debug=4
1976+
aventen_s3_sync.menu.DebugLevel.verbose=Verbose
1977+
aventen_s3_sync.menu.DebugLevel.verbose.build.code_debug=5
1978+
1979+
aventen_s3_sync.menu.EraseFlash.none=Disabled
1980+
aventen_s3_sync.menu.EraseFlash.none.upload.erase_cmd=
1981+
aventen_s3_sync.menu.EraseFlash.all=Enabled
1982+
aventen_s3_sync.menu.EraseFlash.all.upload.erase_cmd=-e
1983+
1984+
##############################################################
1985+
17701986
tinypico.name=UM TinyPICO
17711987

17721988
tinypico.bootloader.tool=esptool_py

‎variants/Aventen_S3_Sync/pins_arduino.h‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
#ifndef Pins_Arduino_h
2+
#define Pins_Arduino_h
3+
4+
#include <stdint.h>
5+
#include "soc/soc_caps.h"
6+
7+
#define USB_VID 0x303a
8+
#define USB_PID 0x1001
9+
#define USB_MANUFACTURER "Aventen"
10+
#define USB_PRODUCT "Aventen S3 Sync"
11+
#define USB_SERIAL ""
12+
13+
#define NUM_DIGITAL_PINS SOC_GPIO_PIN_COUNT // GPIO 0..48
14+
#define NUM_ANALOG_INPUTS 20 // GPIO 1..20
15+
#define EXTERNAL_NUM_INTERRUPTS NUM_DIGITAL_PINS // All GPIOs
16+
17+
#define analogInputToDigitalPin(p) (((p)<NUM_ANALOG_INPUTS)?(analogChannelToDigitalPin(p)):-1)
18+
#define digitalPinToInterrupt(p) (((p)<NUM_DIGITAL_PINS)?(p):NOT_AN_INTERRUPT)
19+
#define digitalPinHasPWM(p) (p < NUM_DIGITAL_PINS)
20+
21+
static const uint8_t TX = 43;
22+
static const uint8_t RX = 44;
23+
24+
static const uint8_t SDA = 2;
25+
static const uint8_t SCL = 3;
26+
static const uint8_t SCL_1 = 21;
27+
static const uint8_t SDA_1 = 20;
28+
29+
static const uint8_t SS = 10;
30+
static const uint8_t MOSI = 11;
31+
static const uint8_t MISO = 13;
32+
static const uint8_t SCK = 12;
33+
34+
static const uint8_t ALS = 17;
35+
static const uint8_t RGB_DI = 38;
36+
static const uint8_t RF_SW = 37;
37+
38+
static const uint8_t A0 = 1;
39+
static const uint8_t A1 = 2;
40+
static const uint8_t A2 = 3;
41+
static const uint8_t A3 = 4;
42+
static const uint8_t A4 = 5;
43+
static const uint8_t A5 = 6;
44+
static const uint8_t A6 = 7;
45+
static const uint8_t A7 = 8;
46+
static const uint8_t A8 = 9;
47+
static const uint8_t A9 = 10;
48+
static const uint8_t A10 = 11;
49+
static const uint8_t A11 = 12;
50+
static const uint8_t A12 = 13;
51+
static const uint8_t A13 = 14;
52+
static const uint8_t A14 = 15;
53+
static const uint8_t A15 = 16;
54+
55+
static const uint8_t T1 = 1;
56+
static const uint8_t T2 = 2;
57+
static const uint8_t T3 = 3;
58+
static const uint8_t T4 = 4;
59+
static const uint8_t T5 = 5;
60+
static const uint8_t T6 = 6;
61+
static const uint8_t T7 = 7;
62+
static const uint8_t T8 = 8;
63+
static const uint8_t T9 = 9;
64+
static const uint8_t T10 = 10;
65+
static const uint8_t T11 = 11;
66+
static const uint8_t T12 = 12;
67+
static const uint8_t T13 = 13;
68+
static const uint8_t T14 = 14;
69+
static const uint8_t T15 = 15;
70+
71+
#endif /* Pins_Arduino_h */

0 commit comments

Comments
 (0)