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1 parent 6669da7 commit 7f0d5baCopy full SHA for 7f0d5ba
scripts/dtsi-gen.py
@@ -6,7 +6,7 @@ def cpu_template (id):
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compatible = "riscv";
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reg = <{id}>;
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riscv,isa = "rv32ima";
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- mmu-type = "riscv,rv32";
+ mmu-type = "riscv,sv32";
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cpu{id}_intc: interrupt-controller {{
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#interrupt-cells = <1>;
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#address-cells = <0>;
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