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Merge pull request #525 from visitorckw/add-bitmanip-extension-support
Add bitmanip extension support
2 parents 5b90d0f + 73dea0c commit f69d9dd

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11 files changed

+988
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11 files changed

+988
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‎.ci/riscv-tests.sh‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,3 +19,4 @@ make ENABLE_EXT_M=1 ENABLE_EXT_A=1 ENABLE_EXT_F=1 ENABLE_EXT_C=1 \
1919
ENABLE_Zicsr=1 ENABLE_Zifencei=1 ENABLE_FULL4G=1
2020
make arch-test RISCV_DEVICE=IMAFCZicsrZifencei || exit 1
2121
make arch-test RISCV_DEVICE=FCZicsr || exit 1
22+
make arch-test RISCV_DEVICE=IMZbaZbbZbcZbs || exit 1

‎Makefile‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,22 @@ $(call set-feature, Zicsr)
107107
ENABLE_Zifencei ?= 1
108108
$(call set-feature, Zifencei)
109109

110+
# Zba Address generation instructions
111+
ENABLE_Zba ?= 1
112+
$(call set-feature, Zba)
113+
114+
# Zbb Basic bit-manipulation
115+
ENABLE_Zbb ?= 1
116+
$(call set-feature, Zbb)
117+
118+
# Zbc Carry-less multiplication
119+
ENABLE_Zbc ?= 1
120+
$(call set-feature, Zbc)
121+
122+
# Zbs Single-bit instructions
123+
ENABLE_Zbs ?= 1
124+
$(call set-feature, Zbs)
125+
110126
ENABLE_FULL4G ?= 0
111127

112128
# Experimental SDL oriented system calls

‎README.md‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ a focus on efficiency and readability.
2424

2525
Features:
2626
* Fast interpreter for executing the RV32 ISA
27-
* Comprehensive support for RV32I and M, A, F, C extensions
27+
* Comprehensive support for RV32I and M, A, F, C, Zba, Zbb, Zbc, Zbs extensions
2828
* Memory-efficient design
2929
* Built-in ELF loader
3030
* Implementation of commonly used newlib system calls
@@ -120,6 +120,10 @@ The image containing all the necessary tools for development and testing can be
120120
* `ENABLE_EXT_A`: Standard Extension for Atomic Instructions
121121
* `ENABLE_EXT_F`: Standard Extension for Single-Precision Floating Point Instructions
122122
* `ENABLE_EXT_C`: Standard Extension for Compressed Instructions (RV32C.D excluded)
123+
* `ENABLE_Zba`: Standard Extension for Address Generation Instructions
124+
* `ENABLE_Zbb`: Standard Extension for Basic Bit-Manipulation Instructions
125+
* `ENABLE_Zbc`: Standard Extension for Carry-Less Multiplication Instructions
126+
* `ENABLE_Zbs`: Standard Extension for Single-Bit Instructions
123127
* `ENABLE_Zicsr`: Control and Status Register (CSR)
124128
* `ENABLE_Zifencei`: Instruction-Fetch Fence
125129
* `ENABLE_GDBSTUB` : GDB remote debugging support
@@ -187,6 +191,10 @@ Current progress of this emulator in riscv-arch-test (RV32):
187191
- `A`: Standard Extension for Atomic Instructions
188192
- `F`: Standard Extension for Single-Precision Floating-Point
189193
- `C`: Standard Extension for Compressed Instruction
194+
- `Zba`: Standard Extension for Address Generation Instructions
195+
- `Zbb`: Standard Extension for Basic Bit-Manipulation
196+
- `Zbc`: Standard Extension for Carry-Less Multiplication
197+
- `Zbs`: Standard Extension for Single-Bit Instructions
190198
- `Zifencei`: Instruction-Fetch Fence
191199
- `privilege`: RISCV Privileged Specification
192200

‎src/common.h‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,63 @@ static inline int rv_clz(uint32_t v)
7272
}
7373
#endif
7474

75+
#if defined(_MSC_VER)
76+
#include <intrin.h>
77+
static inline int rv_ctz(uint32_t v)
78+
{
79+
/* 0 is considered as undefined behavior */
80+
assert(v);
81+
82+
uint32_t trailing_zero = 0;
83+
_BitScanForward(&trailing_zero, v);
84+
return trailing_zero;
85+
}
86+
#elif defined(__GNUC__) || defined(__clang__)
87+
static inline int rv_ctz(uint32_t v)
88+
{
89+
/* https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html */
90+
/* 0 is considered as undefined behavior */
91+
assert(v);
92+
93+
return __builtin_ctz(v);
94+
}
95+
#else /* generic implementation */
96+
static inline int rv_ctz(uint32_t v)
97+
{
98+
/* 0 is considered as undefined behavior */
99+
assert(v);
100+
101+
/* https://graphics.stanford.edu/~seander/bithacks.html#ZerosOnRightMultLookup
102+
*/
103+
104+
static const int mul_debruijn[32] = {
105+
0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8,
106+
31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9};
107+
108+
return mul_debruijn[((uint32_t) ((v & -v) * 0x077CB531U)) >> 27];
109+
}
110+
#endif
111+
112+
#if defined(__GNUC__) || defined(__clang__)
113+
static inline int rv_popcount(uint32_t v)
114+
{
115+
/* https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html */
116+
117+
return __builtin_popcount(v);
118+
}
119+
#else /* generic implementation */
120+
static inline int rv_popcount(uint32_t v)
121+
{
122+
/* https://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
123+
*/
124+
125+
v -= (v >> 1) & 0x55555555;
126+
v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
127+
v = (v + (v >> 4)) & 0x0f0f0f0f;
128+
return (v * 0x01010101) >> 24;
129+
}
130+
#endif
131+
75132
/*
76133
* Integer log base 2
77134
*

‎src/decode.c‎

Lines changed: 179 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -464,6 +464,42 @@ static inline bool op_op_imm(rv_insn_t *ir, const uint32_t insn)
464464
ir->opcode = rv_insn_addi;
465465
break;
466466
case 1: /* SLLI: Shift Left Logical */
467+
#if RV32_HAS(Zbb)
468+
if (ir->imm == 0b011000000000) { /* clz */
469+
ir->opcode = rv_insn_clz;
470+
return true;
471+
}
472+
if (ir->imm == 0b011000000001) { /* ctz */
473+
ir->opcode = rv_insn_ctz;
474+
return true;
475+
}
476+
if (ir->imm == 0b011000000010) { /* cpop */
477+
ir->opcode = rv_insn_cpop;
478+
return true;
479+
}
480+
if (ir->imm == 0b011000000100) { /* sext.b */
481+
ir->opcode = rv_insn_sextb;
482+
return true;
483+
}
484+
if (ir->imm == 0b011000000101) { /* sext.h */
485+
ir->opcode = rv_insn_sexth;
486+
return true;
487+
}
488+
#endif
489+
#if RV32_HAS(Zbs)
490+
if (ir->imm >> 5 == 0b0100100) { /* bclri */
491+
ir->opcode = rv_insn_bclri;
492+
return true;
493+
}
494+
if (ir->imm >> 5 == 0b0110100) { /* binvi */
495+
ir->opcode = rv_insn_binvi;
496+
return true;
497+
}
498+
if (ir->imm >> 5 == 0b0010100) { /* bseti */
499+
ir->opcode = rv_insn_bseti;
500+
return true;
501+
}
502+
#endif
467503
ir->opcode = rv_insn_slli;
468504
if (unlikely(ir->imm & (1 << 5)))
469505
return false;
@@ -478,6 +514,26 @@ static inline bool op_op_imm(rv_insn_t *ir, const uint32_t insn)
478514
ir->opcode = rv_insn_xori;
479515
break;
480516
case 5:
517+
#if RV32_HAS(Zbb)
518+
if (ir->imm >> 5 == 0b0110000) { /* rori */
519+
ir->opcode = rv_insn_rori;
520+
return true;
521+
}
522+
if (ir->imm == 0b001010000111) { /* orc.b */
523+
ir->opcode = rv_insn_orcb;
524+
return true;
525+
}
526+
if (ir->imm == 0b011010011000) { /* rev8 */
527+
ir->opcode = rv_insn_rev8;
528+
return true;
529+
}
530+
#endif
531+
#if RV32_HAS(Zbs)
532+
if (ir->imm >> 5 == 0b0100100) { /* bexti */
533+
ir->opcode = rv_insn_bexti;
534+
return true;
535+
}
536+
#endif
481537
/* SLL, SRL, and SRA perform logical left, logical right, and
482538
* arithmetic right shifts on the value in register rs1.
483539
*/
@@ -665,6 +721,117 @@ static inline bool op_op(rv_insn_t *ir, const uint32_t insn)
665721
break;
666722
#endif /* RV32_HAS(EXT_M) */
667723

724+
#if RV32_HAS(Zba)
725+
/* inst funct7 rs2 rs1 funct3 rd opcode
726+
* ------+-------+---+---+------+--+-------
727+
* SH1ADD 0010000 rs2 rs1 010 rd 0110011
728+
* SH2ADD 0010000 rs2 rs1 100 rd 0110011
729+
* SH3ADD 0010000 rs2 rs1 110 rd 0110011
730+
*/
731+
case 0b0010000:
732+
switch (funct3) {
733+
case 0b010: /* sh1add */
734+
ir->opcode = rv_insn_sh1add;
735+
break;
736+
case 0b100: /* sh2add */
737+
ir->opcode = rv_insn_sh2add;
738+
break;
739+
case 0b110: /* sh3add */
740+
ir->opcode = rv_insn_sh3add;
741+
break;
742+
default: /* illegal instruction */
743+
return false;
744+
}
745+
break;
746+
#endif /* RV32_HAS(Zba) */
747+
748+
#if RV32_HAS(Zbb) || RV32_HAS(Zbc)
749+
/* inst funct7 rs2 rs1 funct3 rd opcode
750+
* ------+-------+---+---+------+--+-------
751+
* MAX 0000101 rs2 rs1 110 rd 0110011
752+
* MIN 0000101 rs2 rs1 100 rd 0110011
753+
* MAXU 0000101 rs2 rs1 111 rd 0110011
754+
* MINU 0000101 rs2 rs1 101 rd 0110011
755+
* ROL 0110000 rs2 rs1 001 rd 0110011
756+
* ROR 0110000 rs2 rs1 101 rd 0110011
757+
*/
758+
case 0b0000101:
759+
switch (funct3) {
760+
#if RV32_HAS(Zbb)
761+
case 0b110: /* max */
762+
ir->opcode = rv_insn_max;
763+
break;
764+
case 0b100: /* min */
765+
ir->opcode = rv_insn_min;
766+
break;
767+
case 0b111: /* maxu */
768+
ir->opcode = rv_insn_maxu;
769+
break;
770+
case 0b101: /* minu */
771+
ir->opcode = rv_insn_minu;
772+
break;
773+
#endif
774+
#if RV32_HAS(Zbc)
775+
case 0b001: /*clmul */
776+
ir->opcode = rv_insn_clmul;
777+
break;
778+
case 0b011: /*clmulh */
779+
ir->opcode = rv_insn_clmulh;
780+
break;
781+
case 0b010: /*clmulr */
782+
ir->opcode = rv_insn_clmulr;
783+
break;
784+
#endif
785+
default: /* illegal instruction */
786+
return false;
787+
}
788+
break;
789+
#endif
790+
#if RV32_HAS(Zbb)
791+
case 0b0110000:
792+
switch (funct3) {
793+
case 0b001: /* rol */
794+
ir->opcode = rv_insn_rol;
795+
break;
796+
case 0b101: /* ror */
797+
ir->opcode = rv_insn_ror;
798+
break;
799+
default: /* illegal instruction */
800+
return false;
801+
}
802+
break;
803+
case 0b0000100:
804+
if (unlikely(ir->rs2))
805+
return false;
806+
ir->opcode = rv_insn_zexth;
807+
break;
808+
#endif /* RV32_HAS(Zbb) */
809+
810+
#if RV32_HAS(Zbs)
811+
case 0b0100100:
812+
switch (funct3) {
813+
case 0b001: /* bclr */
814+
ir->opcode = rv_insn_bclr;
815+
break;
816+
case 0b101: /* bext */
817+
ir->opcode = rv_insn_bext;
818+
break;
819+
default: /* illegal instruction */
820+
return false;
821+
}
822+
break;
823+
case 0b0110100:
824+
if (unlikely(funct3 != 0b001))
825+
return false;
826+
ir->opcode = rv_insn_binv;
827+
break;
828+
case 0b0010100:
829+
if (unlikely(funct3 != 0b001))
830+
return false;
831+
ir->opcode = rv_insn_bset;
832+
break;
833+
#endif /* RV32_HAS(Zbs) */
834+
668835
case 0b0100000:
669836
switch (funct3) {
670837
case 0b000: /* SUB: Substract */
@@ -673,6 +840,18 @@ static inline bool op_op(rv_insn_t *ir, const uint32_t insn)
673840
case 0b101: /* SRA: Shift Right Arithmetic */
674841
ir->opcode = rv_insn_sra;
675842
break;
843+
#if RV32_HAS(Zbb)
844+
case 0b111: /* ANDN */
845+
ir->opcode = rv_insn_andn;
846+
break;
847+
case 0b110: /* ORN */
848+
ir->opcode = rv_insn_orn;
849+
break;
850+
case 0b100: /* XNOR */
851+
ir->opcode = rv_insn_xnor;
852+
break;
853+
#endif /* RV32_HAS(Zbb) */
854+
676855
default: /* illegal instruction */
677856
return false;
678857
}

‎src/decode.h‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,50 @@ enum op_field {
9797
_(csrrsi, 0, 4, 0, ENC(rs1, rd)) \
9898
_(csrrci, 0, 4, 0, ENC(rs1, rd)) \
9999
) \
100+
/* RV32 Zba Standard Extension */ \
101+
IIF(RV32_HAS(Zba))( \
102+
_(sh1add, 0, 4, 0, ENC(rs1, rs2, rd)) \
103+
_(sh2add, 0, 4, 0, ENC(rs1, rs2, rd)) \
104+
_(sh3add, 0, 4, 0, ENC(rs1, rs2, rd)) \
105+
) \
106+
/* RV32 Zbb Standard Extension */ \
107+
IIF(RV32_HAS(Zbb))( \
108+
_(andn, 0, 4, 0, ENC(rs1, rs2, rd)) \
109+
_(orn, 0, 4, 0, ENC(rs1, rs2, rd)) \
110+
_(xnor, 0, 4, 0, ENC(rs1, rs2, rd)) \
111+
_(clz, 0, 4, 0, ENC(rs1, rd)) \
112+
_(ctz, 0, 4, 0, ENC(rs1, rd)) \
113+
_(cpop, 0, 4, 0, ENC(rs1, rd)) \
114+
_(max, 0, 4, 0, ENC(rs1, rs2, rd)) \
115+
_(maxu, 0, 4, 0, ENC(rs1, rs2, rd)) \
116+
_(min, 0, 4, 0, ENC(rs1, rs2, rd)) \
117+
_(minu, 0, 4, 0, ENC(rs1, rs2, rd)) \
118+
_(sextb, 0, 4, 0, ENC(rs1, rd)) \
119+
_(sexth, 0, 4, 0, ENC(rs1, rd)) \
120+
_(zexth, 0, 4, 0, ENC(rs1, rd)) \
121+
_(rol, 0, 4, 0, ENC(rs1, rs2, rd)) \
122+
_(ror, 0, 4, 0, ENC(rs1, rs2, rd)) \
123+
_(rori, 0, 4, 0, ENC(rs1, rd)) \
124+
_(orcb, 0, 4, 0, ENC(rs1, rd)) \
125+
_(rev8, 0, 4, 0, ENC(rs1, rd)) \
126+
) \
127+
/* RV32 Zbc Standard Extension */ \
128+
IIF(RV32_HAS(Zbc))( \
129+
_(clmul, 0, 4, 0, ENC(rs1, rs2, rd)) \
130+
_(clmulh, 0, 4, 0, ENC(rs1, rs2, rd)) \
131+
_(clmulr, 0, 4, 0, ENC(rs1, rs2, rd)) \
132+
) \
133+
/* RV32 Zbs Standard Extension */ \
134+
IIF(RV32_HAS(Zbs))( \
135+
_(bclr, 0, 4, 0, ENC(rs1, rs2, rd)) \
136+
_(bclri, 0, 4, 0, ENC(rs1, rs2, rd)) \
137+
_(bext, 0, 4, 0, ENC(rs1, rs2, rd)) \
138+
_(bexti, 0, 4, 0, ENC(rs1, rs2, rd)) \
139+
_(binv, 0, 4, 0, ENC(rs1, rs2, rd)) \
140+
_(binvi, 0, 4, 0, ENC(rs1, rs2, rd)) \
141+
_(bset, 0, 4, 0, ENC(rs1, rs2, rd)) \
142+
_(bseti, 0, 4, 0, ENC(rs1, rs2, rd)) \
143+
) \
100144
/* RV32M Standard Extension */ \
101145
IIF(RV32_HAS(EXT_M))( \
102146
_(mul, 0, 4, 1, ENC(rs1, rs2, rd)) \

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