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CI: Add JIT architecture test
The JIT architecture test enables "ARCH_TEST" feature, and the build process of Sail RISC-V model is removed from the GitHub Actions.
1 parent 5ec905a commit 5fd922c

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12 files changed

+83
-44
lines changed

12 files changed

+83
-44
lines changed

.ci/common.sh

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
check_platform()
33
{
44
MACHINE_TYPE=`uname -m`
5-
if [ ${MACHINE_TYPE} != 'x86_64' ]; then
5+
if [ ${MACHINE_TYPE} != 'x86_64' ] && [ ${MACHINE_TYPE} != 'aarch64' ]; then
66
exit 1
77
fi
88

.ci/riscv-tests.sh

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,17 @@ make distclean
1717
# necessary. We need to investigate why full 4 GiB memory access is required
1818
# for this purpose, although the emulator can run all selected benchmarks with
1919
# much smaller memory mapping regions.
20-
make ENABLE_EXT_M=1 ENABLE_EXT_A=1 ENABLE_EXT_F=1 ENABLE_EXT_C=1 \
20+
make ENABLE_ARCH_TEST=1 ENABLE_EXT_M=1 ENABLE_EXT_A=1 ENABLE_EXT_F=1 ENABLE_EXT_C=1 \
2121
ENABLE_Zicsr=1 ENABLE_Zifencei=1 ENABLE_FULL4G=1 $PARALLEL
22-
make arch-test RISCV_DEVICE=IMAFCZicsrZifencei $PARALLEL || exit 1
23-
make arch-test RISCV_DEVICE=FCZicsr $PARALLEL || exit 1
24-
make arch-test RISCV_DEVICE=IMZbaZbbZbcZbs $PARALLEL || exit 1
22+
make arch-test RISCV_DEVICE=IMAFCZicsrZifencei HW_DATA_MISALIGN=1 $PARALLEL || exit 1
23+
make arch-test RISCV_DEVICE=FCZicsr HW_DATA_MISALIGN=1 $PARALLEL || exit 1
24+
make arch-test RISCV_DEVICE=IMZbaZbbZbcZbs HW_DATA_MISALIGN=1 $PARALLEL || exit 1
25+
26+
# Rebuild with JIT
27+
# Do not run the architecture test with "Zicsr" extension. It ignores
28+
# the hardware misalignment (hw_data_misaligned_support) option.
29+
make distclean
30+
make ENABLE_ARCH_TEST=1 ENABLE_JIT=1 ENABLE_T2C=0 \
31+
ENABLE_EXT_M=1 ENABLE_EXT_A=1 ENABLE_EXT_F=1 ENABLE_EXT_C=1 \
32+
ENABLE_Zicsr=1 ENABLE_Zifencei=1 ENABLE_FULL4G=1 $PARALLEL
33+
make arch-test RISCV_DEVICE=IMC HW_DATA_MISALIGN=0 $PARALLEL || exit 1

.ci/riscv-toolchain-install.sh

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,12 @@ mkdir -p toolchain
1111
if [[ "$#" == "0" ]] || [[ "$1" != "riscv-collab" ]]; then
1212
GCC_VER=14.2.0-2
1313
TOOLCHAIN_REPO=https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
14-
TOOLCHAIN_URL=${TOOLCHAIN_REPO}/releases/download/v${GCC_VER}/xpack-riscv-none-elf-gcc-${GCC_VER}-linux-x64.tar.gz
14+
15+
if [[ ${MACHINE_TYPE} == "x86_64" ]]; then
16+
TOOLCHAIN_URL=${TOOLCHAIN_REPO}/releases/download/v${GCC_VER}/xpack-riscv-none-elf-gcc-${GCC_VER}-linux-x64.tar.gz
17+
elif [[ ${MACHINE_TYPE} == "aarch64" ]]; then
18+
TOOLCHAIN_URL=${TOOLCHAIN_REPO}/releases/download/v${GCC_VER}/xpack-riscv-none-elf-gcc-${GCC_VER}-linux-arm64.tar.gz
19+
fi
1520
else
1621
UBUNTU_VER=`lsb_release -r | cut -f2`
1722
GCC_VER=2024.11.22

.github/workflows/build-artifact.yml

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,6 @@ jobs:
110110
sudo apt-get update -q -y
111111
sudo apt-get upgrade -q -y
112112
sudo apt-get install -q -y gcc-multilib g++-multilib
113-
sudo apt-get install -q -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev
114113
.ci/riscv-toolchain-install.sh
115114
echo "$PWD/toolchain/bin" >> $GITHUB_PATH
116115
- name: Build binaries
@@ -120,19 +119,6 @@ jobs:
120119
mv build/sha1sum-linux-x86-softfp /tmp
121120
mv build/sha1sum-riscv32 /tmp
122121
mv build/linux-x86-softfp build/riscv32 /tmp/rv32emu-prebuilt
123-
- name: Build Sail model
124-
run: |
125-
cd /tmp
126-
opam init -y --disable-sandboxing
127-
opam switch create ocaml-base-compiler.4.06.1
128-
opam install sail -y
129-
eval $(opam config env)
130-
git clone https://github.com/riscv/sail-riscv.git
131-
cd sail-riscv
132-
git checkout 9547a30bf84572c458476591b569a95f5232c1c7
133-
ARCH=RV32 make -j
134-
mkdir -p /tmp/rv32emu-prebuilt/sail_cSim
135-
mv c_emulator/riscv_sim_RV32 /tmp/rv32emu-prebuilt/sail_cSim
136122
- name: Create tarball
137123
run: |
138124
cd /tmp

.github/workflows/main.yml

Lines changed: 9 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,12 @@ jobs:
142142
.ci/boot-linux.sh
143143
make ENABLE_SYSTEM=1 clean
144144
if: ${{ always() }}
145+
- name: Architecture test
146+
env:
147+
CC: ${{ steps.install_cc.outputs.cc }}
148+
run: |
149+
.ci/riscv-tests.sh
150+
if: ${{ always() }}
145151

146152
host-arm64:
147153
needs: [detect-code-related-file-changes]
@@ -161,7 +167,7 @@ jobs:
161167
# No 'sudo' is available
162168
install: |
163169
apt-get update -q -y
164-
apt-get install -q -y git build-essential libsdl2-dev libsdl2-mixer-dev lsb-release wget software-properties-common gnupg bc
170+
apt-get install -q -y git build-essential libsdl2-dev libsdl2-mixer-dev lsb-release wget software-properties-common gnupg bc python3 python3-pip
165171
git config --global --add safe.directory ${{ github.workspace }}
166172
git config --global --add safe.directory ${{ github.workspace }}/src/softfloat
167173
git config --global --add safe.directory ${{ github.workspace }}/src/mini-gdbstub
@@ -176,6 +182,8 @@ jobs:
176182
make ENABLE_JIT=1 clean && make ENABLE_EXT_A=0 ENABLE_JIT=1 check -j$(nproc)
177183
make ENABLE_JIT=1 clean && make ENABLE_EXT_F=0 ENABLE_JIT=1 check -j$(nproc)
178184
make ENABLE_JIT=1 clean && make ENABLE_EXT_C=0 ENABLE_JIT=1 check -j$(nproc)
185+
.ci/riscv-toolchain-install.sh && export PATH=$PWD/toolchain/bin:$PATH
186+
.ci/riscv-tests.sh
179187
180188
coding-style:
181189
needs: [detect-code-related-file-changes]
@@ -212,21 +220,6 @@ jobs:
212220
run: |
213221
make ENABLE_JIT=1 distclean && scan-build-18 -v -o ~/scan-build --status-bugs --use-cc=clang-18 --force-analyze-debug-code --show-description -analyzer-config stable-report-filename=true -enable-checker valist,nullability make ENABLE_EXT_F=0 ENABLE_SDL=0 ENABLE_JIT=1
214222
215-
compliance-test:
216-
needs: [detect-code-related-file-changes]
217-
if: needs.detect-code-related-file-changes.outputs.has_code_related_changes == 'true'
218-
runs-on: ubuntu-latest
219-
steps:
220-
- uses: actions/checkout@v4
221-
- name: install-dependencies
222-
run: |
223-
.ci/riscv-toolchain-install.sh
224-
shell: bash
225-
- name: architectural test
226-
run: |
227-
.ci/riscv-tests.sh
228-
shell: bash
229-
230223
# https://docs.docker.com/build/ci/github-actions/multi-platform/
231224
docker-hub-build-and-publish:
232225
needs: [detect-code-related-file-changes]

Makefile

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,9 @@ CFLAGS += -DMEM_SIZE=0x$(REAL_MEM_SIZE) -DDTB_SIZE=0x$(REAL_DTB_SIZE) -DINITRD_S
5858
endif
5959
endif
6060

61+
ENABLE_ARCH_TEST ?= 0
62+
$(call set-feature, ARCH_TEST)
63+
6164
# Enable link-time optimization (LTO)
6265
ENABLE_LTO ?= 1
6366
ifeq ($(call has, LTO), 1)

mk/artifact.mk

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,8 @@ SHELL_HACK := $(shell mkdir -p $(BIN_DIR)/linux-x86-softfp $(BIN_DIR)/riscv32 $(
3939
ifeq ($(call has, PREBUILT), 1)
4040
ifeq ($(call has, SYSTEM), 1)
4141
LATEST_RELEASE := $(shell wget -q https://api.github.com/repos/sysprog21/rv32emu-prebuilt/releases -O- | grep '"tag_name"' | grep "Linux-Image" | head -n 1 | sed -E 's/.*"tag_name": "([^"]+)".*/\1/')
42+
else ifeq ($(call has, ARCH_TEST), 1)
43+
LATEST_RELEASE := $(shell wget -q https://api.github.com/repos/sysprog21/rv32emu-prebuilt/releases -O- | grep '"tag_name"' | grep "sail" | head -n 1 | sed -E 's/.*"tag_name": "([^"]+)".*/\1/')
4244
else
4345
LATEST_RELEASE := $(shell wget -q https://api.github.com/repos/sysprog21/rv32emu-prebuilt/releases -O- | grep '"tag_name"' | grep "ELF" | head -n 1 | sed -E 's/.*"tag_name": "([^"]+)".*/\1/')
4446
endif
@@ -67,6 +69,14 @@ ifeq ($(call has, SYSTEM), 1)
6769
))
6870

6971
$(Q)$(eval RV32EMU_PREBUILT_TARBALL := rv32emu-linux-image-prebuilt.tar.gz)
72+
else ifeq ($(call has, ARCH_TEST), 1)
73+
$(Q)$(eval PREBUILT_SAIL_FILENAME := $(shell cat $(BIN_DIR)/rv32emu-prebuilt-sail-$(HOST_PLATFORM).sha | awk '{ print $$2 };'))
74+
75+
$(Q)$(eval $(foreach FILE,$(PREBUILT_SAIL_FILENAME), \
76+
$(call verify,$(shell grep -w $(FILE) $(BIN_DIR)/rv32emu-prebuilt-sail-$(HOST_PLATFORM).sha | awk '{ print $$1 };'),$(BIN_DIR)/$(FILE),RES) \
77+
))
78+
79+
$(Q)$(eval RV32EMU_PREBUILT_TARBALL := rv32emu-prebuilt-sail-$(HOST_PLATFORM))
7080
else
7181
$(Q)$(eval PREBUILT_X86_FILENAME := $(shell cat $(BIN_DIR)/sha1sum-linux-x86-softfp | awk '{ print $$2 };'))
7282
$(Q)$(eval PREBUILT_RV32_FILENAME := $(shell cat $(BIN_DIR)/sha1sum-riscv32 | awk '{ print $$2 };'))
@@ -81,12 +91,21 @@ else
8191
$(Q)$(eval RV32EMU_PREBUILT_TARBALL := rv32emu-prebuilt.tar.gz)
8292
endif
8393

94+
ifeq ($(call has, ARCH_TEST), 1)
8495
$(Q)if [ "$(RES)" = "1" ]; then \
85-
$(PRINTF) "\n$(YELLOW)SHA-1 verification fails! Re-fetching prebuilt binaries from \"rv32emu-prebuilt\" ...\n$(NO_COLOR)"; \
96+
$(PRINTF) "\n$(YELLOW)SHA-1 verification failed! Re-fetching prebuilt binaries from \"rv32emu-prebuilt\" ...\n$(NO_COLOR)"; \
97+
wget -q --show-progress https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/$(RV32EMU_PREBUILT_TARBALL) -O build/$(RV32EMU_PREBUILT_TARBALL);\
98+
else \
99+
$(call notice, [OK]); \
100+
fi
101+
else
102+
$(Q)if [ "$(RES)" = "1" ]; then \
103+
$(PRINTF) "\n$(YELLOW)SHA-1 verification failed! Re-fetching prebuilt binaries from \"rv32emu-prebuilt\" ...\n$(NO_COLOR)"; \
86104
wget -q --show-progress https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/$(RV32EMU_PREBUILT_TARBALL) -O- | tar -C build --strip-components=1 -xz; \
87105
else \
88106
$(call notice, [OK]); \
89107
fi
108+
endif
90109
else
91110
ifeq ($(call has, SYSTEM), 1)
92111
$(Q)(cd $(BIN_DIR) && $(SHA1SUM) linux-image/Image >> sha1sum-linux-image)
@@ -127,10 +146,12 @@ endif
127146

128147
fetch-checksum:
129148
ifeq ($(call has, PREBUILT), 1)
130-
$(Q)$(PRINTF) "Fetching SHA-1 of prebuilt binaries ... "
149+
$(Q)$(PRINTF) "Fetching SHA-1 of prebuilt binaries ...\n"
131150
ifeq ($(call has, SYSTEM), 1)
132151
$(Q)wget -q -O $(BIN_DIR)/sha1sum-linux-image https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/sha1sum-linux-image
133152
$(Q)$(call notice, [OK])
153+
else ifeq ($(call has, ARCH_TEST), 1)
154+
$(Q)wget -q -O $(BIN_DIR)/rv32emu-prebuilt-sail-$(HOST_PLATFORM).sha https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/rv32emu-prebuilt-sail-$(HOST_PLATFORM).sha
134155
else
135156
$(Q)wget -q -O $(BIN_DIR)/sha1sum-linux-x86-softfp https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/sha1sum-linux-x86-softfp
136157
$(Q)wget -q -O $(BIN_DIR)/sha1sum-riscv32 https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/sha1sum-riscv32

mk/common.mk

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,15 @@ else
55
PRINTF = env printf
66
endif
77

8+
UNAME_M := $(shell uname -m)
9+
ifeq ($(UNAME_M),x86_64)
10+
HOST_PLATFORM := x86
11+
else ifeq ($(UNAME_M),aarch64)
12+
HOST_PLATFORM := aarch64
13+
else
14+
$(error Unsupported platform.)
15+
endif
16+
817
# Control the build verbosity
918
# 'make V=1' equals to 'make VERBOSE=1'
1019
ifeq ("$(origin V)", "command line")

mk/riscv-arch-test.mk

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,9 @@ ifeq ($(CROSS_COMPILE),)
2020
$(error GNU Toolchain for RISC-V is required to build architecture tests. Please check package installation)
2121
endif
2222
git submodule update --init $(dir $(ARCH_TEST_DIR))
23-
$(Q)cp $(OUT)/sail_cSim/riscv_sim_RV32 tests/arch-test-target/sail_cSim/riscv_sim_RV32
24-
$(Q)python3 -B $(RISCV_TARGET)/setup.py --riscv_device=$(RISCV_DEVICE)
23+
$(Q)cp $(OUT)/rv32emu-prebuilt-sail-$(HOST_PLATFORM) tests/arch-test-target/sail_cSim/riscv_sim_RV32
24+
$(Q)chmod +x tests/arch-test-target/sail_cSim/riscv_sim_RV32
25+
$(Q)python3 -B $(RISCV_TARGET)/setup.py --riscv_device=$(RISCV_DEVICE) --hw_data_misalign=$(HW_DATA_MISALIGN)
2526
$(Q)riscof run --work-dir=$(WORK) \
2627
--config=$(RISCV_TARGET)/config.ini \
2728
--suite=$(ARCH_TEST_SUITE) \

src/emulate.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -955,7 +955,7 @@ static block_t *block_find_or_translate(riscv_t *rv)
955955
return next_blk;
956956
}
957957

958-
#if RV32_HAS(JIT)
958+
#if RV32_HAS(JIT) && !RV32_HAS(ARCH_TEST)
959959
static bool runtime_profiler(riscv_t *rv, block_t *block)
960960
{
961961
/* Based on our observations, a significant number of true hotspots are
@@ -1105,7 +1105,11 @@ void rv_step(void *arg)
11051105
prev = NULL;
11061106
continue;
11071107
} /* check if the execution path is potential hotspot */
1108-
if (block->translatable && runtime_profiler(rv, block)) {
1108+
if (block->translatable
1109+
#if !RV32_HAS(ARCH_TEST)
1110+
&& runtime_profiler(rv, block)
1111+
#endif
1112+
) {
11091113
jit_translate(rv, block);
11101114
((exec_block_func_t) state->buf)(
11111115
rv, (uintptr_t) (state->buf + block->offset));

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