Fix csr cycle unasyc

Previous commit 78836cf prevents frequently update of rv->csr_cycle by
manipulate it with register. However, currently rv->csr_cycle only
update after a block end or JIT clearing block map. This results csr
cycle instructions cannot fetch up-to-date cycle. If csr cycle
instructions are located in a same block, leading to the result cycle count
becomes zero.

This commit updates rv->csr_cycle everytime before csr instruction is executed.

Author: Max042004

src/rv32_template.c

@@ -1216,6 +1216,7 @@ RVOP(
 RVOP(
     csrrw,
     {
+	rv->csr_cycle = cycle;
         uint32_t tmp = csr_csrrw(rv, ir->imm, rv->X[ir->rs1]);
         rv->X[ir->rd] = ir->rd ? tmp : rv->X[ir->rd];
     },
@@ -1235,6 +1236,7 @@ RVOP(
 RVOP(
     csrrs,
     {
+	rv->csr_cycle = cycle;
         uint32_t tmp = csr_csrrs(
             rv, ir->imm, (ir->rs1 == rv_reg_zero) ? 0U : rv->X[ir->rs1]);
         rv->X[ir->rd] = ir->rd ? tmp : rv->X[ir->rd];
@@ -1247,6 +1249,7 @@ RVOP(
 RVOP(
     csrrc,
     {
+	rv->csr_cycle = cycle;
         uint32_t tmp = csr_csrrc(
             rv, ir->imm, (ir->rs1 == rv_reg_zero) ? 0U : rv->X[ir->rs1]);
         rv->X[ir->rd] = ir->rd ? tmp : rv->X[ir->rd];
@@ -1259,6 +1262,7 @@ RVOP(
 RVOP(
     csrrwi,
     {
+	rv->csr_cycle = cycle;
         uint32_t tmp = csr_csrrw(rv, ir->imm, ir->rs1);
         rv->X[ir->rd] = ir->rd ? tmp : rv->X[ir->rd];
     },
@@ -1270,6 +1274,7 @@ RVOP(
 RVOP(
     csrrsi,
     {
+	rv->csr_cycle = cycle;
         uint32_t tmp = csr_csrrs(rv, ir->imm, ir->rs1);
         rv->X[ir->rd] = ir->rd ? tmp : rv->X[ir->rd];
     },
@@ -1281,6 +1286,7 @@ RVOP(
 RVOP(
     csrrci,
     {
+	rv->csr_cycle = cycle;
         uint32_t tmp = csr_csrrc(rv, ir->imm, ir->rs1);
         rv->X[ir->rd] = ir->rd ? tmp : rv->X[ir->rd];
     },