Merge pull request #160 from sx-aurora-dev/merge/mor-mand-mxor

Merge/mor mand mxor

Author: kaz7

llvm/lib/Target/VE/VEInstrPatternsVec.td

@@ -76,14 +76,12 @@ def : Pat<(store v512i1:$vx, ADDRrii:$addr),
 
 ///// Mask Arithmetic /////
 
-// Mask arithmetic
-multiclass MaskArith<ValueType MaskVT, string MaskTag="mmm"> {
-  def : Pat<(MaskVT (and MaskVT:$ma, MaskVT:$mb)), (!cast<Instruction>("ANDM"#MaskTag#MaskTag) $ma, $mb)>;
-  def : Pat<(MaskVT (or  MaskVT:$ma, MaskVT:$mb)), (!cast<Instruction>("ORM"#MaskTag#MaskTag)  $ma, $mb)>;
-  def : Pat<(MaskVT (xor MaskVT:$ma, MaskVT:$mb)), (!cast<Instruction>("XORM"#MaskTag#MaskTag) $ma, $mb)>;
-}
+class Mask_Binary<ValueType MaskVT, SDPatternOperator MaskOp, string InstName> :
+  Pat<(MaskVT (MaskOp MaskVT:$ma, MaskVT:$mb)), (!cast<Instruction>(InstName#"mm") $ma, $mb)>;
 
-defm: MaskArith<v256i1,"m">;
+def: Mask_Binary<v256i1, and, "ANDM">;
+def: Mask_Binary<v256i1, or,  "ORM">;
+def: Mask_Binary<v256i1, xor, "XORM">;
 
 // FIXME: Valid but very inefficient (incurs repetitive unpacking and packing).
 // split pattern (unpack splice, pack)
@@ -242,7 +240,6 @@ defm : vbrd_elem64<v512f32, i64, simm7, LO7>;
 defm : vbrd_elem64<v512i32, f64, simm7fp, LO7FP>;
 defm : vbrd_elem64<v512f32, f64, simm7fp, LO7FP>;
 
-
 ///// vec_seq /////
 
 def: Pat<(v512i32 (vec_seq i32:$vl)),
@@ -440,3 +437,4 @@ def : Pat<(v512i1 (vec_broadcast (i32 0), (i32 512))),
 //   def : Pat<(store v256f64:$vx, I64:$addr),
 //             (VSTirvl 8, $addr, v256f64:$vx, (VLEN 256))>;
 // }
+

llvm/test/CodeGen/VE/Vector/mask_binary.ll

@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+; Function Attrs: nounwind
+define fastcc <256 x i1> @and_mm_v256i1(<256 x i1> %x, <256 x i1> %y) {
+; CHECK-LABEL: and_mm_v256i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andm %vm1, %vm1, %vm2
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = and <256 x i1> %x, %y
+  ret <256 x i1> %z
+}
+
+; Function Attrs: nounwind
+define fastcc <256 x i1> @or_mm_v256i1(<256 x i1> %x, <256 x i1> %y) {
+; CHECK-LABEL: or_mm_v256i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    orm %vm1, %vm1, %vm2
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = or <256 x i1> %x, %y
+  ret <256 x i1> %z
+}
+
+; Function Attrs: nounwind
+define fastcc <256 x i1> @xor_mm_v256i1(<256 x i1> %x, <256 x i1> %y) {
+; CHECK-LABEL: xor_mm_v256i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorm %vm1, %vm1, %vm2
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = xor <256 x i1> %x, %y
+  ret <256 x i1> %z
+}
+