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[AArch64] Improve lowering of scalar abs(sub(a, b)). (llvm#151180)
This patch avoids a comparison against zero when lowering abs(sub(a, b)) patterns, instead reusing the condition codes generated by a subs of the operands directly. For example, currently: ``` sxtb w8, w0 sub w8, w8, w1, sxtb cmp w8, #0 cneg w0, w8, mi ``` becomes: ``` sxtb w8, w0 subs w8, w8, w1, sxtb cneg w0, w8, mi ``` Together with llvm#151177, this should handle the remaining patterns in llvm#118413.
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7 files changed

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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25455,6 +25455,29 @@ static SDValue performCSELCombine(SDNode *N,
2545525455
}
2545625456
}
2545725457

25458+
// CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y) if cc doesn't
25459+
// use overflow flags, to avoid the comparison with zero. In case of success,
25460+
// this also replaces the original SUB(x,y) with the newly created SUBS(x,y).
25461+
// NOTE: Perhaps in the future use performFlagSettingCombine to replace SUB
25462+
// nodes with their SUBS equivalent as is already done for other flag-setting
25463+
// operators, in which case doing the replacement here becomes redundant.
25464+
if (Cond.getOpcode() == AArch64ISD::SUBS && Cond->hasNUsesOfValue(1, 1) &&
25465+
isNullConstant(Cond.getOperand(1))) {
25466+
SDValue Sub = Cond.getOperand(0);
25467+
AArch64CC::CondCode CC =
25468+
static_cast<AArch64CC::CondCode>(N->getConstantOperandVal(2));
25469+
if (Sub.getOpcode() == ISD::SUB &&
25470+
(CC == AArch64CC::EQ || CC == AArch64CC::NE || CC == AArch64CC::MI ||
25471+
CC == AArch64CC::PL)) {
25472+
SDLoc DL(N);
25473+
SDValue Subs = DAG.getNode(AArch64ISD::SUBS, DL, Cond->getVTList(),
25474+
Sub.getOperand(0), Sub.getOperand(1));
25475+
DCI.CombineTo(Sub.getNode(), Subs);
25476+
DCI.CombineTo(Cond.getNode(), Subs, Subs.getValue(1));
25477+
return SDValue(N, 0);
25478+
}
25479+
}
25480+
2545825481
// CSEL (LASTB P, Z), X, NE(ANY P) -> CLASTB P, X, Z
2545925482
if (SDValue CondLast = foldCSELofLASTB(N, DAG))
2546025483
return CondLast;

‎llvm/test/CodeGen/AArch64/abds-neg.ll‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: sxtb w8, w0
12-
; CHECK-NEXT: sub w8, w8, w1, sxtb
13-
; CHECK-NEXT: cmp w8, #0
12+
; CHECK-NEXT: subs w8, w8, w1, sxtb
1413
; CHECK-NEXT: cneg w0, w8, pl
1514
; CHECK-NEXT: ret
1615
%aext = sext i8 %a to i64
@@ -26,8 +25,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2625
; CHECK-LABEL: abd_ext_i8_i16:
2726
; CHECK: // %bb.0:
2827
; CHECK-NEXT: sxtb w8, w0
29-
; CHECK-NEXT: sub w8, w8, w1, sxth
30-
; CHECK-NEXT: cmp w8, #0
28+
; CHECK-NEXT: subs w8, w8, w1, sxth
3129
; CHECK-NEXT: cneg w0, w8, pl
3230
; CHECK-NEXT: ret
3331
%aext = sext i8 %a to i64
@@ -43,8 +41,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4341
; CHECK-LABEL: abd_ext_i8_undef:
4442
; CHECK: // %bb.0:
4543
; CHECK-NEXT: sxtb w8, w0
46-
; CHECK-NEXT: sub w8, w8, w1, sxtb
47-
; CHECK-NEXT: cmp w8, #0
44+
; CHECK-NEXT: subs w8, w8, w1, sxtb
4845
; CHECK-NEXT: cneg w0, w8, pl
4946
; CHECK-NEXT: ret
5047
%aext = sext i8 %a to i64
@@ -60,8 +57,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
6057
; CHECK-LABEL: abd_ext_i16:
6158
; CHECK: // %bb.0:
6259
; CHECK-NEXT: sxth w8, w0
63-
; CHECK-NEXT: sub w8, w8, w1, sxth
64-
; CHECK-NEXT: cmp w8, #0
60+
; CHECK-NEXT: subs w8, w8, w1, sxth
6561
; CHECK-NEXT: cneg w0, w8, pl
6662
; CHECK-NEXT: ret
6763
%aext = sext i16 %a to i64
@@ -93,8 +89,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
9389
; CHECK-LABEL: abd_ext_i16_undef:
9490
; CHECK: // %bb.0:
9591
; CHECK-NEXT: sxth w8, w0
96-
; CHECK-NEXT: sub w8, w8, w1, sxth
97-
; CHECK-NEXT: cmp w8, #0
92+
; CHECK-NEXT: subs w8, w8, w1, sxth
9893
; CHECK-NEXT: cneg w0, w8, pl
9994
; CHECK-NEXT: ret
10095
%aext = sext i16 %a to i64

‎llvm/test/CodeGen/AArch64/abds.ll‎

Lines changed: 12 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: sxtb w8, w0
12-
; CHECK-NEXT: sub w8, w8, w1, sxtb
13-
; CHECK-NEXT: cmp w8, #0
12+
; CHECK-NEXT: subs w8, w8, w1, sxtb
1413
; CHECK-NEXT: cneg w0, w8, mi
1514
; CHECK-NEXT: ret
1615
%aext = sext i8 %a to i64
@@ -25,8 +24,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2524
; CHECK-LABEL: abd_ext_i8_i16:
2625
; CHECK: // %bb.0:
2726
; CHECK-NEXT: sxtb w8, w0
28-
; CHECK-NEXT: sub w8, w8, w1, sxth
29-
; CHECK-NEXT: cmp w8, #0
27+
; CHECK-NEXT: subs w8, w8, w1, sxth
3028
; CHECK-NEXT: cneg w0, w8, mi
3129
; CHECK-NEXT: ret
3230
%aext = sext i8 %a to i64
@@ -41,8 +39,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4139
; CHECK-LABEL: abd_ext_i8_undef:
4240
; CHECK: // %bb.0:
4341
; CHECK-NEXT: sxtb w8, w0
44-
; CHECK-NEXT: sub w8, w8, w1, sxtb
45-
; CHECK-NEXT: cmp w8, #0
42+
; CHECK-NEXT: subs w8, w8, w1, sxtb
4643
; CHECK-NEXT: cneg w0, w8, mi
4744
; CHECK-NEXT: ret
4845
%aext = sext i8 %a to i64
@@ -57,8 +54,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
5754
; CHECK-LABEL: abd_ext_i16:
5855
; CHECK: // %bb.0:
5956
; CHECK-NEXT: sxth w8, w0
60-
; CHECK-NEXT: sub w8, w8, w1, sxth
61-
; CHECK-NEXT: cmp w8, #0
57+
; CHECK-NEXT: subs w8, w8, w1, sxth
6258
; CHECK-NEXT: cneg w0, w8, mi
6359
; CHECK-NEXT: ret
6460
%aext = sext i16 %a to i64
@@ -88,8 +84,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
8884
; CHECK-LABEL: abd_ext_i16_undef:
8985
; CHECK: // %bb.0:
9086
; CHECK-NEXT: sxth w8, w0
91-
; CHECK-NEXT: sub w8, w8, w1, sxth
92-
; CHECK-NEXT: cmp w8, #0
87+
; CHECK-NEXT: subs w8, w8, w1, sxth
9388
; CHECK-NEXT: cneg w0, w8, mi
9489
; CHECK-NEXT: ret
9590
%aext = sext i16 %a to i64
@@ -215,8 +210,7 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
215210
; CHECK-LABEL: abd_minmax_i8:
216211
; CHECK: // %bb.0:
217212
; CHECK-NEXT: sxtb w8, w0
218-
; CHECK-NEXT: sub w8, w8, w1, sxtb
219-
; CHECK-NEXT: cmp w8, #0
213+
; CHECK-NEXT: subs w8, w8, w1, sxtb
220214
; CHECK-NEXT: cneg w0, w8, mi
221215
; CHECK-NEXT: ret
222216
%min = call i8 @llvm.smin.i8(i8 %a, i8 %b)
@@ -229,8 +223,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
229223
; CHECK-LABEL: abd_minmax_i16:
230224
; CHECK: // %bb.0:
231225
; CHECK-NEXT: sxth w8, w0
232-
; CHECK-NEXT: sub w8, w8, w1, sxth
233-
; CHECK-NEXT: cmp w8, #0
226+
; CHECK-NEXT: subs w8, w8, w1, sxth
234227
; CHECK-NEXT: cneg w0, w8, mi
235228
; CHECK-NEXT: ret
236229
%min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
@@ -287,8 +280,7 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
287280
; CHECK-LABEL: abd_cmp_i8:
288281
; CHECK: // %bb.0:
289282
; CHECK-NEXT: sxtb w8, w0
290-
; CHECK-NEXT: sub w8, w8, w1, sxtb
291-
; CHECK-NEXT: cmp w8, #0
283+
; CHECK-NEXT: subs w8, w8, w1, sxtb
292284
; CHECK-NEXT: cneg w0, w8, mi
293285
; CHECK-NEXT: ret
294286
%cmp = icmp sgt i8 %a, %b
@@ -302,8 +294,7 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
302294
; CHECK-LABEL: abd_cmp_i16:
303295
; CHECK: // %bb.0:
304296
; CHECK-NEXT: sxth w8, w0
305-
; CHECK-NEXT: sub w8, w8, w1, sxth
306-
; CHECK-NEXT: cmp w8, #0
297+
; CHECK-NEXT: subs w8, w8, w1, sxth
307298
; CHECK-NEXT: cneg w0, w8, mi
308299
; CHECK-NEXT: ret
309300
%cmp = icmp sge i16 %a, %b
@@ -508,9 +499,8 @@ define i64 @vector_legalized(i16 %a, i16 %b) {
508499
; CHECK: // %bb.0:
509500
; CHECK-NEXT: movi v0.2d, #0000000000000000
510501
; CHECK-NEXT: sxth w8, w0
511-
; CHECK-NEXT: sub w8, w8, w1, sxth
502+
; CHECK-NEXT: subs w8, w8, w1, sxth
512503
; CHECK-NEXT: addp d0, v0.2d
513-
; CHECK-NEXT: cmp w8, #0
514504
; CHECK-NEXT: cneg w8, w8, mi
515505
; CHECK-NEXT: fmov x9, d0
516506
; CHECK-NEXT: add x0, x9, x8
@@ -533,8 +523,7 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
533523
; CHECK-LABEL: abd_select_i8:
534524
; CHECK: // %bb.0:
535525
; CHECK-NEXT: sxtb w8, w0
536-
; CHECK-NEXT: sub w8, w8, w1, sxtb
537-
; CHECK-NEXT: cmp w8, #0
526+
; CHECK-NEXT: subs w8, w8, w1, sxtb
538527
; CHECK-NEXT: cneg w0, w8, mi
539528
; CHECK-NEXT: ret
540529
%cmp = icmp slt i8 %a, %b
@@ -548,8 +537,7 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
548537
; CHECK-LABEL: abd_select_i16:
549538
; CHECK: // %bb.0:
550539
; CHECK-NEXT: sxth w8, w0
551-
; CHECK-NEXT: sub w8, w8, w1, sxth
552-
; CHECK-NEXT: cmp w8, #0
540+
; CHECK-NEXT: subs w8, w8, w1, sxth
553541
; CHECK-NEXT: cneg w0, w8, mi
554542
; CHECK-NEXT: ret
555543
%cmp = icmp sle i16 %a, %b

‎llvm/test/CodeGen/AArch64/abdu-neg.ll‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: and w8, w0, #0xff
12-
; CHECK-NEXT: sub w8, w8, w1, uxtb
13-
; CHECK-NEXT: cmp w8, #0
12+
; CHECK-NEXT: subs w8, w8, w1, uxtb
1413
; CHECK-NEXT: cneg w0, w8, pl
1514
; CHECK-NEXT: ret
1615
%aext = zext i8 %a to i64
@@ -26,8 +25,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2625
; CHECK-LABEL: abd_ext_i8_i16:
2726
; CHECK: // %bb.0:
2827
; CHECK-NEXT: and w8, w0, #0xff
29-
; CHECK-NEXT: sub w8, w8, w1, uxth
30-
; CHECK-NEXT: cmp w8, #0
28+
; CHECK-NEXT: subs w8, w8, w1, uxth
3129
; CHECK-NEXT: cneg w0, w8, pl
3230
; CHECK-NEXT: ret
3331
%aext = zext i8 %a to i64
@@ -43,8 +41,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4341
; CHECK-LABEL: abd_ext_i8_undef:
4442
; CHECK: // %bb.0:
4543
; CHECK-NEXT: and w8, w0, #0xff
46-
; CHECK-NEXT: sub w8, w8, w1, uxtb
47-
; CHECK-NEXT: cmp w8, #0
44+
; CHECK-NEXT: subs w8, w8, w1, uxtb
4845
; CHECK-NEXT: cneg w0, w8, pl
4946
; CHECK-NEXT: ret
5047
%aext = zext i8 %a to i64
@@ -60,8 +57,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
6057
; CHECK-LABEL: abd_ext_i16:
6158
; CHECK: // %bb.0:
6259
; CHECK-NEXT: and w8, w0, #0xffff
63-
; CHECK-NEXT: sub w8, w8, w1, uxth
64-
; CHECK-NEXT: cmp w8, #0
60+
; CHECK-NEXT: subs w8, w8, w1, uxth
6561
; CHECK-NEXT: cneg w0, w8, pl
6662
; CHECK-NEXT: ret
6763
%aext = zext i16 %a to i64
@@ -93,8 +89,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
9389
; CHECK-LABEL: abd_ext_i16_undef:
9490
; CHECK: // %bb.0:
9591
; CHECK-NEXT: and w8, w0, #0xffff
96-
; CHECK-NEXT: sub w8, w8, w1, uxth
97-
; CHECK-NEXT: cmp w8, #0
92+
; CHECK-NEXT: subs w8, w8, w1, uxth
9893
; CHECK-NEXT: cneg w0, w8, pl
9994
; CHECK-NEXT: ret
10095
%aext = zext i16 %a to i64

‎llvm/test/CodeGen/AArch64/abdu.ll‎

Lines changed: 13 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: and w8, w0, #0xff
12-
; CHECK-NEXT: sub w8, w8, w1, uxtb
13-
; CHECK-NEXT: cmp w8, #0
12+
; CHECK-NEXT: subs w8, w8, w1, uxtb
1413
; CHECK-NEXT: cneg w0, w8, mi
1514
; CHECK-NEXT: ret
1615
%aext = zext i8 %a to i64
@@ -25,8 +24,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2524
; CHECK-LABEL: abd_ext_i8_i16:
2625
; CHECK: // %bb.0:
2726
; CHECK-NEXT: and w8, w0, #0xff
28-
; CHECK-NEXT: sub w8, w8, w1, uxth
29-
; CHECK-NEXT: cmp w8, #0
27+
; CHECK-NEXT: subs w8, w8, w1, uxth
3028
; CHECK-NEXT: cneg w0, w8, mi
3129
; CHECK-NEXT: ret
3230
%aext = zext i8 %a to i64
@@ -41,8 +39,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4139
; CHECK-LABEL: abd_ext_i8_undef:
4240
; CHECK: // %bb.0:
4341
; CHECK-NEXT: and w8, w0, #0xff
44-
; CHECK-NEXT: sub w8, w8, w1, uxtb
45-
; CHECK-NEXT: cmp w8, #0
42+
; CHECK-NEXT: subs w8, w8, w1, uxtb
4643
; CHECK-NEXT: cneg w0, w8, mi
4744
; CHECK-NEXT: ret
4845
%aext = zext i8 %a to i64
@@ -57,8 +54,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
5754
; CHECK-LABEL: abd_ext_i16:
5855
; CHECK: // %bb.0:
5956
; CHECK-NEXT: and w8, w0, #0xffff
60-
; CHECK-NEXT: sub w8, w8, w1, uxth
61-
; CHECK-NEXT: cmp w8, #0
57+
; CHECK-NEXT: subs w8, w8, w1, uxth
6258
; CHECK-NEXT: cneg w0, w8, mi
6359
; CHECK-NEXT: ret
6460
%aext = zext i16 %a to i64
@@ -88,8 +84,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
8884
; CHECK-LABEL: abd_ext_i16_undef:
8985
; CHECK: // %bb.0:
9086
; CHECK-NEXT: and w8, w0, #0xffff
91-
; CHECK-NEXT: sub w8, w8, w1, uxth
92-
; CHECK-NEXT: cmp w8, #0
87+
; CHECK-NEXT: subs w8, w8, w1, uxth
9388
; CHECK-NEXT: cneg w0, w8, mi
9489
; CHECK-NEXT: ret
9590
%aext = zext i16 %a to i64
@@ -219,8 +214,7 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
219214
; CHECK-LABEL: abd_minmax_i8:
220215
; CHECK: // %bb.0:
221216
; CHECK-NEXT: and w8, w0, #0xff
222-
; CHECK-NEXT: sub w8, w8, w1, uxtb
223-
; CHECK-NEXT: cmp w8, #0
217+
; CHECK-NEXT: subs w8, w8, w1, uxtb
224218
; CHECK-NEXT: cneg w0, w8, mi
225219
; CHECK-NEXT: ret
226220
%min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
@@ -233,8 +227,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
233227
; CHECK-LABEL: abd_minmax_i16:
234228
; CHECK: // %bb.0:
235229
; CHECK-NEXT: and w8, w0, #0xffff
236-
; CHECK-NEXT: sub w8, w8, w1, uxth
237-
; CHECK-NEXT: cmp w8, #0
230+
; CHECK-NEXT: subs w8, w8, w1, uxth
238231
; CHECK-NEXT: cneg w0, w8, mi
239232
; CHECK-NEXT: ret
240233
%min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
@@ -293,8 +286,7 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
293286
; CHECK-LABEL: abd_cmp_i8:
294287
; CHECK: // %bb.0:
295288
; CHECK-NEXT: and w8, w0, #0xff
296-
; CHECK-NEXT: sub w8, w8, w1, uxtb
297-
; CHECK-NEXT: cmp w8, #0
289+
; CHECK-NEXT: subs w8, w8, w1, uxtb
298290
; CHECK-NEXT: cneg w0, w8, mi
299291
; CHECK-NEXT: ret
300292
%cmp = icmp ugt i8 %a, %b
@@ -308,8 +300,7 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
308300
; CHECK-LABEL: abd_cmp_i16:
309301
; CHECK: // %bb.0:
310302
; CHECK-NEXT: and w8, w0, #0xffff
311-
; CHECK-NEXT: sub w8, w8, w1, uxth
312-
; CHECK-NEXT: cmp w8, #0
303+
; CHECK-NEXT: subs w8, w8, w1, uxth
313304
; CHECK-NEXT: cneg w0, w8, mi
314305
; CHECK-NEXT: ret
315306
%cmp = icmp uge i16 %a, %b
@@ -373,10 +364,9 @@ define i64 @vector_legalized(i16 %a, i16 %b) {
373364
; CHECK: // %bb.0:
374365
; CHECK-NEXT: movi v0.2d, #0000000000000000
375366
; CHECK-NEXT: and w8, w0, #0xffff
376-
; CHECK-NEXT: sub w8, w8, w1, uxth
377-
; CHECK-NEXT: cmp w8, #0
378-
; CHECK-NEXT: addp d0, v0.2d
367+
; CHECK-NEXT: subs w8, w8, w1, uxth
379368
; CHECK-NEXT: cneg w8, w8, mi
369+
; CHECK-NEXT: addp d0, v0.2d
380370
; CHECK-NEXT: fmov x9, d0
381371
; CHECK-NEXT: add x0, x9, x8
382372
; CHECK-NEXT: ret
@@ -398,8 +388,7 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
398388
; CHECK-LABEL: abd_select_i8:
399389
; CHECK: // %bb.0:
400390
; CHECK-NEXT: and w8, w0, #0xff
401-
; CHECK-NEXT: sub w8, w8, w1, uxtb
402-
; CHECK-NEXT: cmp w8, #0
391+
; CHECK-NEXT: subs w8, w8, w1, uxtb
403392
; CHECK-NEXT: cneg w0, w8, mi
404393
; CHECK-NEXT: ret
405394
%cmp = icmp ult i8 %a, %b
@@ -413,8 +402,7 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
413402
; CHECK-LABEL: abd_select_i16:
414403
; CHECK: // %bb.0:
415404
; CHECK-NEXT: and w8, w0, #0xffff
416-
; CHECK-NEXT: sub w8, w8, w1, uxth
417-
; CHECK-NEXT: cmp w8, #0
405+
; CHECK-NEXT: subs w8, w8, w1, uxth
418406
; CHECK-NEXT: cneg w0, w8, mi
419407
; CHECK-NEXT: ret
420408
%cmp = icmp ule i16 %a, %b

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