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Merge commit 'f5c1b5206cbe' from llvm.org/release/21.x into stable/21.x
2 parents 148a7f9 + f5c1b52 commit bfa60e6

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llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15327,6 +15327,12 @@ SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
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}
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}
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// Convert PromOps to handles before doing any RAUW operations, as these
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// may CSE with existing nodes, deleting the originals.
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std::list<HandleSDNode> PromOpHandles;
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for (auto &PromOp : PromOps)
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PromOpHandles.emplace_back(PromOp);
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// Replace all inputs, either with the truncation operand, or a
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// truncation or extension to the final output type.
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for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
@@ -15350,10 +15356,6 @@ SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
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DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
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}
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std::list<HandleSDNode> PromOpHandles;
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for (auto &PromOp : PromOps)
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PromOpHandles.emplace_back(PromOp);
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// Replace all operations (these are all the same, but have a different
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// (promoted) return type). DAG.getNode will validate that the types of
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// a binary operator match, so go through the list in reverse so that
Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; Make sure this does not crash.
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define i32 @test(i32 %arg) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 4, 3, 13, 19, 19
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; CHECK-NEXT: rlwinm 3, 3, 2, 30, 30
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; CHECK-NEXT: xori 4, 4, 4096
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; CHECK-NEXT: xori 3, 3, 2
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; CHECK-NEXT: rlwimi 3, 4, 0, 31, 29
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; CHECK-NEXT: blr
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%icmp = icmp sgt i32 %arg, -1
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%select = select i1 %icmp, i16 1, i16 0
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%select1 = select i1 %icmp, i16 16384, i16 0
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%lshr = lshr i16 %select1, 1
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%zext = zext i16 %lshr to i32
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%lshr2 = lshr i32 %zext, 1
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%shl = shl i16 %select, 1
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%zext3 = zext i16 %shl to i32
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%or = or i32 %lshr2, %zext3
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ret i32 %or
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}

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