Skip to content

Commit 439eca0

Browse files
cparatacparata
committed
Add static random address support for all ST BLE chips
1 parent ed10763 commit 439eca0

File tree

4 files changed

+829
-22
lines changed

4 files changed

+829
-22
lines changed

‎src/utility/HCISharedMemTransport.cpp‎

Lines changed: 196 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -48,11 +48,17 @@ volatile uint16_t _write_index; /* fifo position when receiving */
4848
/* var of different device steps during init and receiving */
4949
volatile bool phase_bd_addr;
5050
volatile bool phase_tx_power;
51+
volatile bool phase_gatt_init;
52+
volatile bool phase_gap_init;
53+
volatile bool phase_random_addr;
54+
volatile bool phase_get_random_addr;
5155
volatile bool phase_reset;
5256
volatile bool phase_running;
57+
volatile bool is_random_addr_msg;
5358

5459
/** Bluetooth Device Address */
5560
static uint8_t bd_addr_udn[CONFIG_DATA_PUBADDR_LEN];
61+
static uint8_t helper_random_addr[6];
5662

5763
/* Private functions ---------------------------------------------------------*/
5864
/**
@@ -175,12 +181,21 @@ void evt_received(TL_EvtPacket_t *hcievt)
175181
* the Reset packet is handled at HCI layer : the running_phase begins
176182
*/
177183
if (phase_running == false) {
178-
/* check the Rx event of complete the previous bd_addr opcode 0xFC0C */
184+
/* check the Rx event of complete the previous bd_addr or random address opcode 0xFC0C */
179185
if ((hcievt->evtserial.evt.evtcode == TL_BLEEVT_CC_OPCODE) &&
180186
(hcievt->evtserial.evt.payload[0] == 0x01) &&
181187
(hcievt->evtserial.evt.payload[1] == 0x0C) &&
182188
(hcievt->evtserial.evt.payload[2] == 0xFC)) {
183-
phase_bd_addr = true;
189+
/* First setting must be global address and is_random_addr_msg should be false
190+
* Second setting must be static random address and is_random_addr_msg should be true
191+
*/
192+
if(!is_random_addr_msg) {
193+
phase_bd_addr = true;
194+
is_random_addr_msg = true;
195+
} else {
196+
phase_random_addr = true;
197+
is_random_addr_msg = false;
198+
}
184199
if (hcievt->evtserial.evt.payload[3] != 0) {
185200
#if defined(PRINT_IPCC_INFO)
186201
printf("Error: wrong BD Addr\r\n");
@@ -203,6 +218,50 @@ void evt_received(TL_EvtPacket_t *hcievt)
203218
/* rx data is no more useful : not stored in the _rxbuff */
204219
break;
205220
}
221+
/* check the Rx event of complete the previous gatt init 0xFD01 */
222+
if ((hcievt->evtserial.evt.evtcode == TL_BLEEVT_CC_OPCODE) &&
223+
(hcievt->evtserial.evt.payload[0] == 0x01) &&
224+
(hcievt->evtserial.evt.payload[1] == 0x01) &&
225+
(hcievt->evtserial.evt.payload[2] == 0xFD)) {
226+
phase_gatt_init = true;
227+
if (hcievt->evtserial.evt.payload[3] != 0) {
228+
#if defined(PRINT_IPCC_INFO)
229+
printf("Error: wrong Random Addr\r\n");
230+
#endif /*(PRINT_IPCC_INFO)*/
231+
}
232+
/* rx data is no more useful : not stored in the _rxbuff */
233+
break;
234+
}
235+
/* check the Rx event of complete the previous gap init 0xFC8A */
236+
if ((hcievt->evtserial.evt.evtcode == TL_BLEEVT_CC_OPCODE) &&
237+
(hcievt->evtserial.evt.payload[0] == 0x01) &&
238+
(hcievt->evtserial.evt.payload[1] == 0x8A) &&
239+
(hcievt->evtserial.evt.payload[2] == 0xFC)) {
240+
phase_gap_init = true;
241+
if (hcievt->evtserial.evt.payload[3] != 0) {
242+
#if defined(PRINT_IPCC_INFO)
243+
printf("Error: wrong Random Addr\r\n");
244+
#endif /*(PRINT_IPCC_INFO)*/
245+
}
246+
/* rx data is no more useful : not stored in the _rxbuff */
247+
break;
248+
}
249+
/* check the Rx event of complete the previous get random addr opcode 0xFC0D */
250+
if ((hcievt->evtserial.evt.evtcode == TL_BLEEVT_CC_OPCODE) &&
251+
(hcievt->evtserial.evt.payload[0] == 0x01) &&
252+
(hcievt->evtserial.evt.payload[1] == 0x0D) &&
253+
(hcievt->evtserial.evt.payload[2] == 0xFC)) {
254+
if (hcievt->evtserial.evt.payload[3] != 0) {
255+
#if defined(PRINT_IPCC_INFO)
256+
printf("Error: wrong Random Addr\r\n");
257+
#endif /*(PRINT_IPCC_INFO)*/
258+
}
259+
260+
memcpy(helper_random_addr, &hcievt->evtserial.evt.payload[5], 6);
261+
phase_get_random_addr = true;
262+
/* rx data is no more useful : not stored in the _rxbuff */
263+
break;
264+
}
206265
/* check if the reset phase is in progress (opcode is 0x0C03) */
207266
if ((hcievt->evtserial.evt.evtcode == TL_BLEEVT_CC_OPCODE) &&
208267
(hcievt->evtserial.evt.payload[0] == 0x01) &&
@@ -389,8 +448,13 @@ HCISharedMemTransportClass::HCISharedMemTransportClass()
389448

390449
phase_bd_addr = false;
391450
phase_tx_power = false;
451+
phase_gatt_init = false;
452+
phase_gap_init = false;
453+
phase_random_addr = false;
454+
phase_get_random_addr = false;
392455
phase_reset = false;
393456
phase_running = false;
457+
is_random_addr_msg = false;
394458
}
395459

396460
HCISharedMemTransportClass::~HCISharedMemTransportClass()
@@ -453,8 +517,13 @@ void HCISharedMemTransportClass::end()
453517
/* the HCI RESET command ready to be processed again */
454518
phase_bd_addr = false;
455519
phase_tx_power = false;
520+
phase_gatt_init = false;
521+
phase_gap_init = false;
522+
phase_random_addr = false;
523+
phase_get_random_addr = false;
456524
phase_reset = false;
457525
phase_running = false;
526+
is_random_addr_msg = false;
458527
}
459528

460529
void HCISharedMemTransportClass::wait(unsigned long timeout)
@@ -543,11 +612,34 @@ size_t HCISharedMemTransportClass::write(const uint8_t *data, size_t length)
543612
while (!phase_bd_addr);
544613
/* this sequence is now complete */
545614

615+
/* set the random address */
616+
bt_ipm_set_random_addr();
617+
/* wait for the Rx complete */
618+
while (!phase_random_addr);
619+
546620
/* set the Tx power */
547621
bt_ipm_set_power();
548622
/* wait for the Rx complete */
549623
while (!phase_tx_power);
550624

625+
/* gatt init */
626+
bt_ipm_gatt_init();
627+
/* wait for the Rx complete */
628+
while (!phase_gatt_init);
629+
630+
/* gap init */
631+
bt_ipm_gap_init();
632+
/* wait for the Rx complete */
633+
while (!phase_gap_init);
634+
635+
/* get the random address */
636+
bt_ipm_get_random_addr();
637+
/* wait for the Rx complete */
638+
while (!phase_get_random_addr);
639+
640+
/* Now we can copy the random address and save it in the transport class */
641+
memcpy(_random_addr, helper_random_addr, 6);
642+
551643
/* this sequence is now complete */
552644
phase_running = true;
553645

@@ -725,6 +817,41 @@ int HCISharedMemTransportClass::bt_ipm_set_addr(void)
725817
return 0; /* Error */
726818
}
727819

820+
int HCISharedMemTransportClass::bt_ipm_set_random_addr(void)
821+
{
822+
/* the specific table for set addr is 8 bytes:
823+
* one byte for config_offset
824+
* one byte for length
825+
* 6 bytes for payload */
826+
uint8_t data[4 + 8];
827+
828+
/*
829+
* Static random Address
830+
* The two upper bits shall be set to 1
831+
* The lowest 32bits is read from the UDN to differentiate between devices
832+
* The RNG may be used to provide a random number on each power on
833+
*/
834+
uint32_t srd_bd_addr[2];
835+
836+
phase_random_addr = false;
837+
838+
srd_bd_addr[1] = 0x0000ED6E;
839+
srd_bd_addr[0] = LL_FLASH_GetUDN( );
840+
841+
data[0] = BT_BUF_CMD;
842+
data[1] = uint8_t(ACI_WRITE_CONFIG_DATA_OPCODE & 0x000000FF); /* OCF */
843+
data[2] = uint8_t((ACI_WRITE_CONFIG_DATA_OPCODE & 0x0000FF00) >> 8); /* OGF */
844+
data[3] = 8; /* length of parameters */
845+
/* fill the ACI_HAL_WRITE_CONFIG_DATA with the addr*/
846+
data[4] = 0x2E; /* the offset */
847+
data[5] = 6; /* is the length of the random address */
848+
memcpy(data + 6, srd_bd_addr, 6);
849+
/* send the ACI_HAL_WRITE_CONFIG_DATA */
850+
mbox_write(data[0], 11, &data[1]);
851+
/* now wait for the corresponding Rx event */
852+
return 1; /* success */
853+
}
854+
728855
int HCISharedMemTransportClass::bt_ipm_set_power(void)
729856
{
730857
/* the specific table for power is 2 bytes:
@@ -737,14 +864,79 @@ int HCISharedMemTransportClass::bt_ipm_set_power(void)
737864
data[1] = (uint8_t)(ACI_HAL_SET_TX_POWER_LEVEL & 0x000000FF); /* the OPCODE */
738865
data[2] = (uint8_t)((ACI_HAL_SET_TX_POWER_LEVEL & 0x0000FF00) >> 8);
739866
data[3] = 2; /* the length */
740-
/* fill the ACI_HAL_WRITE_CONFIG_DATA */
867+
/* fill the SET_POWER */
741868
data[4] = 0x01; /* En_High_Power */
742869
data[5] = CFG_TX_POWER; /* PA_level */
743870

744-
/* send the ACI_HAL_WRITE_CONFIG_DATA */
871+
/* send the SET_POWER */
745872
mbox_write(data[0], 5, &data[1]);
746873
/* now wait for the corresponding Rx event */
747874
return 1; /* success */
748875
}
749876

877+
int HCISharedMemTransportClass::bt_ipm_gatt_init(void)
878+
{
879+
/* the specific table for gatt init */
880+
uint8_t data[4];
881+
882+
phase_gatt_init = false;
883+
884+
data[0] = BT_BUF_CMD; /* the type */
885+
data[1] = 0x01; /* the OPCODE */
886+
data[2] = 0xFD;
887+
data[3] = 0; /* the length */
888+
889+
/* send the GATT_INIT */
890+
mbox_write(data[0], 3, &data[1]);
891+
/* now wait for the corresponding Rx event */
892+
return 1; /* success */
893+
}
894+
895+
int HCISharedMemTransportClass::bt_ipm_gap_init(void)
896+
{
897+
/* the specific table for gap init is 3 bytes:
898+
* Role byte, enable_privacy byte, device_name_char_len byte */
899+
uint8_t data[4 + 3];
900+
901+
phase_tx_power = false;
902+
903+
data[0] = BT_BUF_CMD; /* the type */
904+
data[1] = 0x8A; /* the OPCODE */
905+
data[2] = 0xFC;
906+
data[3] = 3; /* the length */
907+
/* fill the GAP_INIT */
908+
data[4] = 0x0F; /* role */
909+
data[5] = 0x00; /* enable_privacy */
910+
data[6] = 0x00; /* device_name_char_len */
911+
912+
/* send the GAP_INIT */
913+
mbox_write(data[0], 6, &data[1]);
914+
/* now wait for the corresponding Rx event */
915+
return 1; /* success */
916+
}
917+
918+
int HCISharedMemTransportClass::bt_ipm_get_random_addr(void)
919+
{
920+
/* the specific table for set addr is 8 bytes:
921+
* one byte for config_offset
922+
* one byte for length
923+
* 6 bytes for payload */
924+
uint8_t data[4 + 1];
925+
926+
phase_get_random_addr = false;
927+
928+
/* create ACI_READ_CONFIG_DATA_OPCODE */
929+
data[0] = BT_BUF_CMD;
930+
data[1] = uint8_t(ACI_READ_CONFIG_DATA_OPCODE & 0x000000FF); /* OCF */
931+
data[2] = uint8_t((ACI_READ_CONFIG_DATA_OPCODE & 0x0000FF00) >> 8); /* OGF */
932+
data[3] = 1; /* length of parameters */
933+
/* fill the ACI_READ_CONFIG_DATA_OPCODE with the offset*/
934+
data[4] = 0x2E; /* the offset */
935+
936+
/* send the ACI_READ_CONFIG_DATA_OPCODE */
937+
mbox_write(data[0], 4, &data[1]);
938+
/* now wait for the corresponding Rx event */
939+
return 1; /* success */
940+
}
941+
750942
#endif /* STM32WBxx */

‎src/utility/HCISharedMemTransport.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,8 +87,13 @@ class HCISharedMemTransportClass : public HCITransportInterface {
8787
int stm32wb_start_ble(void);
8888
int bt_ipm_ble_init(void);
8989
int bt_ipm_set_addr(void);
90+
int bt_ipm_set_random_addr(void);
9091
int bt_ipm_set_power(void);
92+
int bt_ipm_gatt_init(void);
93+
int bt_ipm_gap_init(void);
94+
int bt_ipm_get_random_addr(void);
9195

96+
uint8_t _random_addr[6];
9297
};
9398

9499
#endif /* _HCI_SHARED_MEM_TRANSPORT_H_ */

0 commit comments

Comments
 (0)