Skip to content

Commit 4d1f280

Browse files
fpistmfpistm
authored
Merge pull request #74 from fpistm/ADC_Negative_Input
Skip Negative input analog channels (INN)
2 parents 38df634 + 75b232f commit 4d1f280

File tree

568 files changed

+18029
-26157
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

568 files changed

+18029
-26157
lines changed

‎src/genpinmap/Arduino/STM32H7xx/STM32H723VEHx/PeripheralPins.c‎

Lines changed: 31 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -32,50 +32,37 @@
3232

3333
#ifdef HAL_ADC_MODULE_ENABLED
3434
WEAK const PinMap PinMap_ADC[] = {
35-
{PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16
36-
{PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INN16
37-
{PA_1_ALT1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17
38-
{PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14
39-
{PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14
40-
{PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15
41-
{PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15
42-
{PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18
43-
{PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18
44-
{PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INN18
45-
{PA_5_ALT1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19
46-
{PA_5_ALT2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INN18
47-
{PA_5_ALT3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19
48-
{PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3
49-
{PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3
50-
{PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INN3
51-
{PA_7_ALT1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7
52-
{PA_7_ALT2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INN3
53-
{PA_7_ALT3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7
54-
{PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INN5
55-
{PB_0_ALT1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9
56-
{PB_0_ALT2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INN5
57-
{PB_0_ALT3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9
58-
{PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5
59-
{PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5
60-
{PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10
61-
{PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10
62-
{PC_0_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10
63-
{PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INN10
64-
{PC_1_ALT1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11
65-
{PC_1_ALT2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INN10
66-
{PC_1_ALT3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11
67-
{PC_1_ALT4, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INN10
68-
{PC_1_ALT5, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11
69-
{PC_2_C, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INN1
70-
{PC_2_C_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0
71-
{PC_3_C, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1
72-
{PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4
73-
{PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4
74-
{PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INN4
75-
{PC_5_ALT1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8
76-
{PC_5_ALT2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INN4
77-
{PC_5_ALT3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8
78-
{NC, NP, 0}
35+
{PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16
36+
{PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17
37+
{PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14
38+
{PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14
39+
{PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15
40+
{PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15
41+
{PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18
42+
{PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18
43+
{PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19
44+
{PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19
45+
{PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3
46+
{PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3
47+
{PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7
48+
{PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7
49+
{PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9
50+
{PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9
51+
{PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5
52+
{PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5
53+
{PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10
54+
{PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10
55+
{PC_0_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10
56+
{PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11
57+
{PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11
58+
{PC_1_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11
59+
{PC_2_C, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0
60+
{PC_3_C, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1
61+
{PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4
62+
{PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4
63+
{PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8
64+
{PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8
65+
{NC, NP, 0}
7966
};
8067
#endif
8168

‎src/genpinmap/Arduino/STM32H7xx/STM32H723VEHx/PinNamesVar.h‎

Lines changed: 58 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -1,73 +1,64 @@
11
/* Dual pad pin name */
2-
PC_2_C = PC_2 | PDUAL,
3-
PC_3_C = PC_3 | PDUAL,
2+
PC_2_C = PC_2 | PDUAL,
3+
PC_3_C = PC_3 | PDUAL,
44

55
/* Alternate pin name */
6-
PA_0_ALT1 = PA_0 | ALT1,
7-
PA_1_ALT1 = PA_1 | ALT1,
8-
PA_1_ALT2 = PA_1 | ALT2,
9-
PA_2_ALT1 = PA_2 | ALT1,
10-
PA_2_ALT2 = PA_2 | ALT2,
11-
PA_3_ALT1 = PA_3 | ALT1,
12-
PA_3_ALT2 = PA_3 | ALT2,
13-
PA_4_ALT1 = PA_4 | ALT1,
14-
PA_4_ALT2 = PA_4 | ALT2,
15-
PA_5_ALT1 = PA_5 | ALT1,
16-
PA_5_ALT2 = PA_5 | ALT2,
17-
PA_5_ALT3 = PA_5 | ALT3,
18-
PA_6_ALT1 = PA_6 | ALT1,
19-
PA_7_ALT1 = PA_7 | ALT1,
20-
PA_7_ALT2 = PA_7 | ALT2,
21-
PA_7_ALT3 = PA_7 | ALT3,
22-
PA_8_ALT1 = PA_8 | ALT1,
23-
PA_9_ALT1 = PA_9 | ALT1,
24-
PA_10_ALT1 = PA_10 | ALT1,
25-
PA_11_ALT1 = PA_11 | ALT1,
26-
PA_12_ALT1 = PA_12 | ALT1,
27-
PA_15_ALT1 = PA_15 | ALT1,
28-
PA_15_ALT2 = PA_15 | ALT2,
29-
PB_0_ALT1 = PB_0 | ALT1,
30-
PB_0_ALT2 = PB_0 | ALT2,
31-
PB_0_ALT3 = PB_0 | ALT3,
32-
PB_1_ALT1 = PB_1 | ALT1,
33-
PB_1_ALT2 = PB_1 | ALT2,
34-
PB_3_ALT1 = PB_3 | ALT1,
35-
PB_3_ALT2 = PB_3 | ALT2,
36-
PB_4_ALT1 = PB_4 | ALT1,
37-
PB_4_ALT2 = PB_4 | ALT2,
38-
PB_5_ALT1 = PB_5 | ALT1,
39-
PB_5_ALT2 = PB_5 | ALT2,
40-
PB_6_ALT1 = PB_6 | ALT1,
41-
PB_6_ALT2 = PB_6 | ALT2,
42-
PB_7_ALT1 = PB_7 | ALT1,
43-
PB_8_ALT1 = PB_8 | ALT1,
44-
PB_8_ALT2 = PB_8 | ALT2,
45-
PB_9_ALT1 = PB_9 | ALT1,
46-
PB_9_ALT2 = PB_9 | ALT2,
47-
PB_14_ALT1 = PB_14 | ALT1,
48-
PB_14_ALT2 = PB_14 | ALT2,
49-
PB_15_ALT1 = PB_15 | ALT1,
50-
PB_15_ALT2 = PB_15 | ALT2,
51-
PC_0_ALT1 = PC_0 | ALT1,
52-
PC_0_ALT2 = PC_0 | ALT2,
53-
PC_1_ALT1 = PC_1 | ALT1,
54-
PC_1_ALT2 = PC_1 | ALT2,
55-
PC_1_ALT3 = PC_1 | ALT3,
56-
PC_1_ALT4 = PC_1 | ALT4,
57-
PC_1_ALT5 = PC_1 | ALT5,
58-
PC_2_C_ALT1 = PC_2_C | ALT1,
59-
PC_4_ALT1 = PC_4 | ALT1,
60-
PC_5_ALT1 = PC_5 | ALT1,
61-
PC_5_ALT2 = PC_5 | ALT2,
62-
PC_5_ALT3 = PC_5 | ALT3,
63-
PC_6_ALT1 = PC_6 | ALT1,
64-
PC_6_ALT2 = PC_6 | ALT2,
65-
PC_7_ALT1 = PC_7 | ALT1,
66-
PC_7_ALT2 = PC_7 | ALT2,
67-
PC_8_ALT1 = PC_8 | ALT1,
68-
PC_9_ALT1 = PC_9 | ALT1,
69-
PC_10_ALT1 = PC_10 | ALT1,
70-
PC_11_ALT1 = PC_11 | ALT1,
6+
PA_0_ALT1 = PA_0 | ALT1,
7+
PA_1_ALT1 = PA_1 | ALT1,
8+
PA_1_ALT2 = PA_1 | ALT2,
9+
PA_2_ALT1 = PA_2 | ALT1,
10+
PA_2_ALT2 = PA_2 | ALT2,
11+
PA_3_ALT1 = PA_3 | ALT1,
12+
PA_3_ALT2 = PA_3 | ALT2,
13+
PA_4_ALT1 = PA_4 | ALT1,
14+
PA_4_ALT2 = PA_4 | ALT2,
15+
PA_5_ALT1 = PA_5 | ALT1,
16+
PA_6_ALT1 = PA_6 | ALT1,
17+
PA_7_ALT1 = PA_7 | ALT1,
18+
PA_7_ALT2 = PA_7 | ALT2,
19+
PA_7_ALT3 = PA_7 | ALT3,
20+
PA_8_ALT1 = PA_8 | ALT1,
21+
PA_9_ALT1 = PA_9 | ALT1,
22+
PA_10_ALT1 = PA_10 | ALT1,
23+
PA_11_ALT1 = PA_11 | ALT1,
24+
PA_12_ALT1 = PA_12 | ALT1,
25+
PA_15_ALT1 = PA_15 | ALT1,
26+
PA_15_ALT2 = PA_15 | ALT2,
27+
PB_0_ALT1 = PB_0 | ALT1,
28+
PB_0_ALT2 = PB_0 | ALT2,
29+
PB_1_ALT1 = PB_1 | ALT1,
30+
PB_1_ALT2 = PB_1 | ALT2,
31+
PB_3_ALT1 = PB_3 | ALT1,
32+
PB_3_ALT2 = PB_3 | ALT2,
33+
PB_4_ALT1 = PB_4 | ALT1,
34+
PB_4_ALT2 = PB_4 | ALT2,
35+
PB_5_ALT1 = PB_5 | ALT1,
36+
PB_5_ALT2 = PB_5 | ALT2,
37+
PB_6_ALT1 = PB_6 | ALT1,
38+
PB_6_ALT2 = PB_6 | ALT2,
39+
PB_7_ALT1 = PB_7 | ALT1,
40+
PB_8_ALT1 = PB_8 | ALT1,
41+
PB_8_ALT2 = PB_8 | ALT2,
42+
PB_9_ALT1 = PB_9 | ALT1,
43+
PB_9_ALT2 = PB_9 | ALT2,
44+
PB_14_ALT1 = PB_14 | ALT1,
45+
PB_14_ALT2 = PB_14 | ALT2,
46+
PB_15_ALT1 = PB_15 | ALT1,
47+
PB_15_ALT2 = PB_15 | ALT2,
48+
PC_0_ALT1 = PC_0 | ALT1,
49+
PC_0_ALT2 = PC_0 | ALT2,
50+
PC_1_ALT1 = PC_1 | ALT1,
51+
PC_1_ALT2 = PC_1 | ALT2,
52+
PC_4_ALT1 = PC_4 | ALT1,
53+
PC_5_ALT1 = PC_5 | ALT1,
54+
PC_6_ALT1 = PC_6 | ALT1,
55+
PC_6_ALT2 = PC_6 | ALT2,
56+
PC_7_ALT1 = PC_7 | ALT1,
57+
PC_7_ALT2 = PC_7 | ALT2,
58+
PC_8_ALT1 = PC_8 | ALT1,
59+
PC_9_ALT1 = PC_9 | ALT1,
60+
PC_10_ALT1 = PC_10 | ALT1,
61+
PC_11_ALT1 = PC_11 | ALT1,
7162

7263
/* SYS_WKUP */
7364
#ifdef PWR_WAKEUP_PIN1

‎src/genpinmap/Arduino/STM32H7xx/STM32H723VEHx/variant.h‎

Lines changed: 56 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -104,71 +104,62 @@ extern "C" {
104104
#define PC3_C A15
105105

106106
// Alternate pins number
107-
#define PA0_ALT1 (PA0 | ALT1)
108-
#define PA1_ALT1 (PA1 | ALT1)
109-
#define PA1_ALT2 (PA1 | ALT2)
110-
#define PA2_ALT1 (PA2 | ALT1)
111-
#define PA2_ALT2 (PA2 | ALT2)
112-
#define PA3_ALT1 (PA3 | ALT1)
113-
#define PA3_ALT2 (PA3 | ALT2)
114-
#define PA4_ALT1 (PA4 | ALT1)
115-
#define PA4_ALT2 (PA4 | ALT2)
116-
#define PA5_ALT1 (PA5 | ALT1)
117-
#define PA5_ALT2 (PA5 | ALT2)
118-
#define PA5_ALT3 (PA5 | ALT3)
119-
#define PA6_ALT1 (PA6 | ALT1)
120-
#define PA7_ALT1 (PA7 | ALT1)
121-
#define PA7_ALT2 (PA7 | ALT2)
122-
#define PA7_ALT3 (PA7 | ALT3)
123-
#define PA8_ALT1 (PA8 | ALT1)
124-
#define PA9_ALT1 (PA9 | ALT1)
125-
#define PA10_ALT1 (PA10 | ALT1)
126-
#define PA11_ALT1 (PA11 | ALT1)
127-
#define PA12_ALT1 (PA12 | ALT1)
128-
#define PA15_ALT1 (PA15 | ALT1)
129-
#define PA15_ALT2 (PA15 | ALT2)
130-
#define PB0_ALT1 (PB0 | ALT1)
131-
#define PB0_ALT2 (PB0 | ALT2)
132-
#define PB0_ALT3 (PB0 | ALT3)
133-
#define PB1_ALT1 (PB1 | ALT1)
134-
#define PB1_ALT2 (PB1 | ALT2)
135-
#define PB3_ALT1 (PB3 | ALT1)
136-
#define PB3_ALT2 (PB3 | ALT2)
137-
#define PB4_ALT1 (PB4 | ALT1)
138-
#define PB4_ALT2 (PB4 | ALT2)
139-
#define PB5_ALT1 (PB5 | ALT1)
140-
#define PB5_ALT2 (PB5 | ALT2)
141-
#define PB6_ALT1 (PB6 | ALT1)
142-
#define PB6_ALT2 (PB6 | ALT2)
143-
#define PB7_ALT1 (PB7 | ALT1)
144-
#define PB8_ALT1 (PB8 | ALT1)
145-
#define PB8_ALT2 (PB8 | ALT2)
146-
#define PB9_ALT1 (PB9 | ALT1)
147-
#define PB9_ALT2 (PB9 | ALT2)
148-
#define PB14_ALT1 (PB14 | ALT1)
149-
#define PB14_ALT2 (PB14 | ALT2)
150-
#define PB15_ALT1 (PB15 | ALT1)
151-
#define PB15_ALT2 (PB15 | ALT2)
152-
#define PC0_ALT1 (PC0 | ALT1)
153-
#define PC0_ALT2 (PC0 | ALT2)
154-
#define PC1_ALT1 (PC1 | ALT1)
155-
#define PC1_ALT2 (PC1 | ALT2)
156-
#define PC1_ALT3 (PC1 | ALT3)
157-
#define PC1_ALT4 (PC1 | ALT4)
158-
#define PC1_ALT5 (PC1 | ALT5)
159-
#define PC2_C_ALT1 (PC2_C | ALT1)
160-
#define PC4_ALT1 (PC4 | ALT1)
161-
#define PC5_ALT1 (PC5 | ALT1)
162-
#define PC5_ALT2 (PC5 | ALT2)
163-
#define PC5_ALT3 (PC5 | ALT3)
164-
#define PC6_ALT1 (PC6 | ALT1)
165-
#define PC6_ALT2 (PC6 | ALT2)
166-
#define PC7_ALT1 (PC7 | ALT1)
167-
#define PC7_ALT2 (PC7 | ALT2)
168-
#define PC8_ALT1 (PC8 | ALT1)
169-
#define PC9_ALT1 (PC9 | ALT1)
170-
#define PC10_ALT1 (PC10 | ALT1)
171-
#define PC11_ALT1 (PC11 | ALT1)
107+
#define PA0_ALT1 (PA0 | ALT1)
108+
#define PA1_ALT1 (PA1 | ALT1)
109+
#define PA1_ALT2 (PA1 | ALT2)
110+
#define PA2_ALT1 (PA2 | ALT1)
111+
#define PA2_ALT2 (PA2 | ALT2)
112+
#define PA3_ALT1 (PA3 | ALT1)
113+
#define PA3_ALT2 (PA3 | ALT2)
114+
#define PA4_ALT1 (PA4 | ALT1)
115+
#define PA4_ALT2 (PA4 | ALT2)
116+
#define PA5_ALT1 (PA5 | ALT1)
117+
#define PA6_ALT1 (PA6 | ALT1)
118+
#define PA7_ALT1 (PA7 | ALT1)
119+
#define PA7_ALT2 (PA7 | ALT2)
120+
#define PA7_ALT3 (PA7 | ALT3)
121+
#define PA8_ALT1 (PA8 | ALT1)
122+
#define PA9_ALT1 (PA9 | ALT1)
123+
#define PA10_ALT1 (PA10 | ALT1)
124+
#define PA11_ALT1 (PA11 | ALT1)
125+
#define PA12_ALT1 (PA12 | ALT1)
126+
#define PA15_ALT1 (PA15 | ALT1)
127+
#define PA15_ALT2 (PA15 | ALT2)
128+
#define PB0_ALT1 (PB0 | ALT1)
129+
#define PB0_ALT2 (PB0 | ALT2)
130+
#define PB1_ALT1 (PB1 | ALT1)
131+
#define PB1_ALT2 (PB1 | ALT2)
132+
#define PB3_ALT1 (PB3 | ALT1)
133+
#define PB3_ALT2 (PB3 | ALT2)
134+
#define PB4_ALT1 (PB4 | ALT1)
135+
#define PB4_ALT2 (PB4 | ALT2)
136+
#define PB5_ALT1 (PB5 | ALT1)
137+
#define PB5_ALT2 (PB5 | ALT2)
138+
#define PB6_ALT1 (PB6 | ALT1)
139+
#define PB6_ALT2 (PB6 | ALT2)
140+
#define PB7_ALT1 (PB7 | ALT1)
141+
#define PB8_ALT1 (PB8 | ALT1)
142+
#define PB8_ALT2 (PB8 | ALT2)
143+
#define PB9_ALT1 (PB9 | ALT1)
144+
#define PB9_ALT2 (PB9 | ALT2)
145+
#define PB14_ALT1 (PB14 | ALT1)
146+
#define PB14_ALT2 (PB14 | ALT2)
147+
#define PB15_ALT1 (PB15 | ALT1)
148+
#define PB15_ALT2 (PB15 | ALT2)
149+
#define PC0_ALT1 (PC0 | ALT1)
150+
#define PC0_ALT2 (PC0 | ALT2)
151+
#define PC1_ALT1 (PC1 | ALT1)
152+
#define PC1_ALT2 (PC1 | ALT2)
153+
#define PC4_ALT1 (PC4 | ALT1)
154+
#define PC5_ALT1 (PC5 | ALT1)
155+
#define PC6_ALT1 (PC6 | ALT1)
156+
#define PC6_ALT2 (PC6 | ALT2)
157+
#define PC7_ALT1 (PC7 | ALT1)
158+
#define PC7_ALT2 (PC7 | ALT2)
159+
#define PC8_ALT1 (PC8 | ALT1)
160+
#define PC9_ALT1 (PC9 | ALT1)
161+
#define PC10_ALT1 (PC10 | ALT1)
162+
#define PC11_ALT1 (PC11 | ALT1)
172163

173164
#define NUM_DIGITAL_PINS 82
174165
#define NUM_DUALPAD_PINS 2

0 commit comments

Comments
 (0)