system(C0) update STM32C0xx HAL Drivers to v1.4.0

Included in STM32CubeC0 FW v1.4.0

Signed-off-by: Frederic Pillon <frederic.pillon@st.com>

Author: fpistm

system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

@@ -472,9 +472,9 @@ extern "C" {
 #define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
 #define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
 #define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7)
+#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
 #define PAGESIZE                      FLASH_PAGE_SIZE
-#endif /* STM32F2 && STM32F4 && STM32F7 &&  STM32H7 */
+#endif /* STM32F2 && STM32F4 && STM32F7 &&  STM32H7 && STM32H5 */
 #define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
 #define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
 #define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
@@ -538,6 +538,10 @@ extern "C" {
 #define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
 #define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
 #endif /* STM32H7 */
+#if defined(STM32H7RS)
+#define FLASH_OPTKEY1                 FLASH_OPT_KEY1
+#define FLASH_OPTKEY2                 FLASH_OPT_KEY2
+#endif /* STM32H7RS */
 #if defined(STM32U5)
 #define OB_USER_nRST_STOP             OB_USER_NRST_STOP
 #define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
@@ -1299,22 +1303,22 @@ extern "C" {
 #define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL
 #endif /* STM32H5 || STM32WBA || STM32H7RS ||  STM32N6 */
 
-#if defined(STM32F7)
+#if defined(STM32F7) || defined(STM32WB)
 #define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
 #define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
-#endif /* STM32F7 */
+#endif /* STM32F7 || STM32WB */
 
 #if defined(STM32H7)
 #define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
 #define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
 #endif /* STM32H7 */
 
-#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
 #define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
 #define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
 #define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
 #define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
-#endif /* STM32F7 || STM32H7 || STM32L0 */
+#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
 
 /**
   * @}
@@ -3946,8 +3950,8 @@ extern "C" {
   */
 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
     defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
-    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \
-    defined (STM32H7RS) ||  defined (STM32U0) || defined (STM32U3)
+    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \
+    defined (STM32U0) || defined (STM32U3)
 #else
 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
 #endif

system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usart.h

@@ -56,6 +56,10 @@ static const uint32_t USART_PRESCALER_TAB[] =
   32UL,
   64UL,
   128UL,
+  256UL,
+  256UL,
+  256UL,
+  256UL,
   256UL
 };
 /**

system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html

@@ -69,19 +69,75 @@ <h1 id="purpose">Purpose</h1>
 <section id="update-history" class="col-sm-12 col-lg-8">
 <h1>Update History</h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section5" checked aria-hidden="true">
-<label for="collapse-section5" checked aria-hidden="true">V1.3.0 /
-30-October-2024</label>
+<input type="checkbox" id="collapse-section6" checked aria-hidden="true">
+<label for="collapse-section6" checked aria-hidden="true">V1.4.0 /
+05-February-2025</label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <ul>
+<li>Maintenance Release of STM32CubeC0 HAL/LL Drivers supporting
+<strong>STM32C011xx/C031xx/C051xx/C071xx/C091xx/C092xx</strong>
+devices</li>
+<li>General updates to fix known defects and implementation
+enhancements</li>
+</ul>
+<h3 id="hal-drivers-updates"><strong>HAL Drivers updates</strong></h3>
+<ul>
+<li>HAL ADC driver:
+<ul>
+<li>Change ADC calibration procedure</li>
+</ul></li>
+<li>HAL RCC driver:
+<ul>
+<li>Add notes to highlight HSI48 clock division factor update limitation
+when HSI48 oscillator is selected as system clock</li>
+</ul></li>
+<li>HAL TIM driver:
+<ul>
+<li>Fix update flag (UIF) clearing in TIM_Base_SetConfig</li>
+</ul></li>
+<li>HAL UART driver:
+<ul>
+<li>Correct references to HAL_UARTEx_WakeupCallback and to
+HAL_UART_WAKEUP_CB_ID define, according to serie capabilities</li>
+<li>Provide accurate position in RxEventCallback when ReceptionToIdle
+mode is used with DMA, when UART and DMA interrupts process is
+delayed</li>
+</ul></li>
+</ul>
+<h3 id="ll-drivers-updates"><strong>LL Drivers updates</strong></h3>
+<ul>
+<li>LL USART driver:
+<ul>
+<li>Solve Coverity out-of-bound memory access warning in use of
+USART_PRESCALER_TAB array</li>
+</ul></li>
+</ul>
+<p>Note: HAL/LL Backward compatibility ensured by legacy defines.</p>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<ul>
+<li>Not applicable</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section5" aria-hidden="true">
+<label for="collapse-section5" aria-hidden="true">V1.3.0 /
+30-October-2024</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
 <li>Official Release of STM32CubeC0 Firmware package supporting
 <strong>STM32C051xx</strong> and <strong>STM32C091/92xx</strong>
 devices</li>
 <li>General updates to fix known defects and implementation
 enhancements</li>
 </ul>
-<h3 id="hal-drivers-updates"><strong>HAL Drivers updates</strong></h3>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers updates</strong></h3>
 <ul>
 <li>HAL generic driver:
 <ul>
@@ -125,7 +181,7 @@ <h3 id="hal-drivers-updates"><strong>HAL Drivers updates</strong></h3>
 polling mode</li>
 </ul></li>
 </ul>
-<h3 id="ll-drivers-updates"><strong>LL Drivers updates</strong></h3>
+<h3 id="ll-drivers-updates-1"><strong>LL Drivers updates</strong></h3>
 <ul>
 <li>LL ADC driver:
 <ul>
@@ -141,11 +197,11 @@ <h3 id="ll-drivers-updates"><strong>LL Drivers updates</strong></h3>
 </ul></li>
 </ul>
 <p>Note: HAL/LL Backward compatibility ensured by legacy defines.</p>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
@@ -156,14 +212,14 @@ <h2 id="backward-compatibility">Backward Compatibility</h2>
 <label for="collapse-section4" aria-hidden="true">V1.2.0 /
 05-June-2024</label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
 <ul>
 <li>Official Release of STM32CubeC0 Firmware package supporting
 <strong>STM32C071xx</strong> devices</li>
 <li>General updates to fix known defects and implementation
 enhancements</li>
 </ul>
-<h3 id="hal-drivers-updates-1"><strong>HAL Drivers updates</strong></h3>
+<h3 id="hal-drivers-updates-2"><strong>HAL Drivers updates</strong></h3>
 <ul>
 <li>HAL generic driver:
 <ul>
@@ -282,7 +338,7 @@ <h3 id="hal-drivers-updates-1"><strong>HAL Drivers updates</strong></h3>
 FIFO reception in Interrupt mode</li>
 </ul></li>
 </ul>
-<h3 id="ll-drivers-updates-1"><strong>LL Drivers updates</strong></h3>
+<h3 id="ll-drivers-updates-2"><strong>LL Drivers updates</strong></h3>
 <ul>
 <li>LL ADC driver:
 <ul>
@@ -336,11 +392,11 @@ <h3 id="ll-drivers-updates-1"><strong>LL Drivers updates</strong></h3>
 </ul></li>
 </ul>
 <p>Note: HAL/LL Backward compatibility ensured by legacy defines.</p>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
@@ -351,7 +407,7 @@ <h2 id="backward-compatibility-1">Backward Compatibility</h2>
 <label for="collapse-section3" aria-hidden="true">V1.1.0 /
 07-June-2023</label>
 <div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <ul>
 <li>Maintenance Release of STM32CubeC0 Firmware Package</li>
 </ul>
@@ -422,9 +478,9 @@ <h2 id="main-changes-2">Main Changes</h2>
 setting.</li>
 </ul></li>
 </ul>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
 <p>N/A</p>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
 <ul>
 <li>HAL_SYSCFG_GetPinBinding() and LL_SYSCFG_GetConfigPinMux() are
 updated.</li>
@@ -436,7 +492,7 @@ <h2 id="backward-compatibility-2">Backward Compatibility</h2>
 <label for="collapse-section2" checked aria-hidden="true">V1.0.1 /
 12-January-2023</label>
 <div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
 <ul>
 <li><p>Patch Release of STM32CubeC0 Firmware Package</p></li>
 <li><p>Update ADC HAL driver with proper internal sensor calibration
@@ -447,7 +503,7 @@ <h2 id="main-changes-3">Main Changes</h2>
 </ul></li>
 <li><p>Update RCC LL driver by adding missing AHB Prescaler.</p></li>
 </ul>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
 <p>N/A</p>
 </div>
 </div>
@@ -456,10 +512,10 @@ <h2 id="known-limitations-3">Known Limitations</h2>
 <label for="collapse-section1" checked aria-hidden="true">V1.0.0 /
 09-February-2022</label>
 <div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
 <p>First official release of HAL and LL drivers for STM32C031xx /
 STM32C011xx devices</p>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
 <p>N/A</p>
 </div>
 </div>

system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c

@@ -56,7 +56,7 @@
   * @brief STM32C0xx HAL Driver version number
    */
 #define __STM32C0xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32C0xx_HAL_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
+#define __STM32C0xx_HAL_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
 #define __STM32C0xx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32C0xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32C0xx_HAL_VERSION         ((__STM32C0xx_HAL_VERSION_MAIN << 24U)\

system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c

@@ -166,11 +166,13 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
           return HAL_ERROR;
         }
       }
-
-      calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance);
+      /* Read the calibration factor and increment by one */
+      calibration_factor_accumulated += (LL_ADC_GetCalibrationFactor(hadc->Instance) + 1UL);
     }
-    /* Compute average */
+    /* Compute average (rounded up to the nearest integer) */
+    calibration_factor_accumulated += (calibration_index / 2UL);
     calibration_factor_accumulated /= calibration_index;
+
     /* Apply calibration factor (requires ADC enable and disable process) */
     LL_ADC_Enable(hadc->Instance);
 

system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c

@@ -164,6 +164,9 @@
 
          (+) The maximum frequency of the SYSCLK, HCLK, PCLK is 48 MHz.
 
+         (+) When the HSI48 oscillator is selected as the System clock (SYSCLK), the number of CPU wait states must
+             be adjusted before any eventual update on the HSI48 clock division factor.
+
   @endverbatim
 
      (++)  Table 1. HCLK clock frequency.
@@ -282,6 +285,9 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not
   *         supported by this function. User should request a transition to LSE Off
   *         first and then to LSE On or LSE Bypass.
+  * @note   When the HSI48 oscillator is selected as the System clock (SYSCLK), the user
+            must adjust the number of CPU wait states in their application (SystemClock_Config() API)
+            before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef  *RCC_OscInitStruct)

system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c

@@ -6956,8 +6956,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
   /* Set the auto-reload preload */
   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 
-  TIMx->CR1 = tmpcr1;
-
   /* Set the Autoreload value */
   TIMx->ARR = (uint32_t)Structure->Period ;
 
@@ -6970,16 +6968,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
     TIMx->RCR = Structure->RepetitionCounter;
   }
 
+  /* Disable Update Event (UEV) with Update Generation (UG)
+     by changing Update Request Source (URS) to avoid Update flag (UIF) */
+  SET_BIT(TIMx->CR1, TIM_CR1_URS);
+
   /* Generate an update event to reload the Prescaler
      and the repetition counter (only for advanced timer) value immediately */
   TIMx->EGR = TIM_EGR_UG;
 
-  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
-  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
-  {
-    /* Clear the update flag */
-    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
-  }
+  TIMx->CR1 = tmpcr1;
 }
 
 /**