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system(L4): update STM32L4xx CMSIS Drivers to v1.7.2
Included in STM32CubeL4 FW v1.17.1 Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
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+1365
-1182
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h‎

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -7,18 +7,17 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - Peripheral's registers declarations and bits definition
10-
* - Macros to access peripheral�s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16-
* All rights reserved.</center></h2>
15+
* Copyright (c) 2017 STMicroelectronics.
16+
* All rights reserved.
1717
*
18-
* This software component is licensed by ST under Apache License, Version 2.0,
19-
* the "License"; You may not use this file except in compliance with the
20-
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/Apache-2.0
18+
* This software is licensed under terms that can be found in the LICENSE file
19+
* in the root directory of this software component.
20+
* If no LICENSE file comes with this software, it is provided AS-IS.
2221
*
2322
******************************************************************************
2423
*/
@@ -45,11 +44,11 @@
4544
/**
4645
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
4746
*/
48-
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
49-
#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
50-
#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
51-
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
52-
#define __FPU_PRESENT 1 /*!< FPU present */
47+
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
48+
#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
49+
#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
50+
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
51+
#define __FPU_PRESENT 1U /*!< FPU present */
5352

5453
/**
5554
* @}
@@ -1011,6 +1010,15 @@ typedef struct
10111010
* @{
10121011
*/
10131012

1013+
/** @addtogroup Hardware_Constant_Definition
1014+
* @{
1015+
*/
1016+
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1017+
1018+
/**
1019+
* @}
1020+
*/
1021+
10141022
/** @addtogroup Peripheral_Registers_Bits_Definition
10151023
* @{
10161024
*/
@@ -1161,7 +1169,7 @@ typedef struct
11611169

11621170
#define ADC_CFGR_ALIGN_Pos (5U)
11631171
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1164-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1172+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
11651173

11661174
#define ADC_CFGR_EXTSEL_Pos (6U)
11671175
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -10910,4 +10918,3 @@ typedef struct
1091010918
* @}
1091110919
*/
1091210920

10913-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h‎

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -7,18 +7,17 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - Peripheral's registers declarations and bits definition
10-
* - Macros to access peripheral�s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16-
* All rights reserved.</center></h2>
15+
* Copyright (c) 2017 STMicroelectronics.
16+
* All rights reserved.
1717
*
18-
* This software component is licensed by ST under Apache License, Version 2.0,
19-
* the "License"; You may not use this file except in compliance with the
20-
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/Apache-2.0
18+
* This software is licensed under terms that can be found in the LICENSE file
19+
* in the root directory of this software component.
20+
* If no LICENSE file comes with this software, it is provided AS-IS.
2221
*
2322
******************************************************************************
2423
*/
@@ -45,11 +44,11 @@
4544
/**
4645
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
4746
*/
48-
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
49-
#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
50-
#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
51-
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
52-
#define __FPU_PRESENT 1 /*!< FPU present */
47+
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
48+
#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
49+
#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
50+
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
51+
#define __FPU_PRESENT 1U /*!< FPU present */
5352

5453
/**
5554
* @}
@@ -1046,6 +1045,15 @@ typedef struct
10461045
* @{
10471046
*/
10481047

1048+
/** @addtogroup Hardware_Constant_Definition
1049+
* @{
1050+
*/
1051+
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1052+
1053+
/**
1054+
* @}
1055+
*/
1056+
10491057
/** @addtogroup Peripheral_Registers_Bits_Definition
10501058
* @{
10511059
*/
@@ -1196,7 +1204,7 @@ typedef struct
11961204

11971205
#define ADC_CFGR_ALIGN_Pos (5U)
11981206
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1199-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1207+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
12001208

12011209
#define ADC_CFGR_EXTSEL_Pos (6U)
12021210
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -11138,4 +11146,3 @@ typedef struct
1113811146
* @}
1113911147
*/
1114011148

11141-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h‎

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -7,18 +7,17 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - Peripheral's registers declarations and bits definition
10-
* - Macros to access peripheral�s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16-
* All rights reserved.</center></h2>
15+
* Copyright (c) 2017 STMicroelectronics.
16+
* All rights reserved.
1717
*
18-
* This software component is licensed by ST under Apache License, Version 2.0,
19-
* the "License"; You may not use this file except in compliance with the
20-
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/Apache-2.0
18+
* This software is licensed under terms that can be found in the LICENSE file
19+
* in the root directory of this software component.
20+
* If no LICENSE file comes with this software, it is provided AS-IS.
2221
*
2322
******************************************************************************
2423
*/
@@ -45,11 +44,11 @@
4544
/**
4645
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
4746
*/
48-
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
49-
#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
50-
#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
51-
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
52-
#define __FPU_PRESENT 1 /*!< FPU present */
47+
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
48+
#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
49+
#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
50+
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
51+
#define __FPU_PRESENT 1U /*!< FPU present */
5352

5453
/**
5554
* @}
@@ -1145,6 +1144,15 @@ typedef struct
11451144
* @{
11461145
*/
11471146

1147+
/** @addtogroup Hardware_Constant_Definition
1148+
* @{
1149+
*/
1150+
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1151+
1152+
/**
1153+
* @}
1154+
*/
1155+
11481156
/** @addtogroup Peripheral_Registers_Bits_Definition
11491157
* @{
11501158
*/
@@ -1295,7 +1303,7 @@ typedef struct
12951303

12961304
#define ADC_CFGR_ALIGN_Pos (5U)
12971305
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1298-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1306+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
12991307

13001308
#define ADC_CFGR_EXTSEL_Pos (6U)
13011309
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -15065,4 +15073,3 @@ typedef struct
1506515073
* @}
1506615074
*/
1506715075

15068-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h‎

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -7,18 +7,17 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - Peripheral's registers declarations and bits definition
10-
* - Macros to access peripheral�s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16-
* All rights reserved.</center></h2>
15+
* Copyright (c) 2017 STMicroelectronics.
16+
* All rights reserved.
1717
*
18-
* This software component is licensed by ST under Apache License, Version 2.0,
19-
* the "License"; You may not use this file except in compliance with the
20-
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/Apache-2.0
18+
* This software is licensed under terms that can be found in the LICENSE file
19+
* in the root directory of this software component.
20+
* If no LICENSE file comes with this software, it is provided AS-IS.
2221
*
2322
******************************************************************************
2423
*/
@@ -45,11 +44,11 @@
4544
/**
4645
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
4746
*/
48-
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
49-
#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
50-
#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
51-
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
52-
#define __FPU_PRESENT 1 /*!< FPU present */
47+
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
48+
#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
49+
#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
50+
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
51+
#define __FPU_PRESENT 1U /*!< FPU present */
5352

5453
/**
5554
* @}
@@ -1130,6 +1129,15 @@ typedef struct
11301129
* @{
11311130
*/
11321131

1132+
/** @addtogroup Hardware_Constant_Definition
1133+
* @{
1134+
*/
1135+
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1136+
1137+
/**
1138+
* @}
1139+
*/
1140+
11331141
/** @addtogroup Peripheral_Registers_Bits_Definition
11341142
* @{
11351143
*/
@@ -1280,7 +1288,7 @@ typedef struct
12801288

12811289
#define ADC_CFGR_ALIGN_Pos (5U)
12821290
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1283-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1291+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
12841292

12851293
#define ADC_CFGR_EXTSEL_Pos (6U)
12861294
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -14859,4 +14867,3 @@ typedef struct
1485914867
* @}
1486014868
*/
1486114869

14862-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h‎

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -7,18 +7,17 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - Peripheral's registers declarations and bits definition
10-
* - Macros to access peripheral�s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16-
* All rights reserved.</center></h2>
15+
* Copyright (c) 2017 STMicroelectronics.
16+
* All rights reserved.
1717
*
18-
* This software component is licensed by ST under Apache License, Version 2.0,
19-
* the "License"; You may not use this file except in compliance with the
20-
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/Apache-2.0
18+
* This software is licensed under terms that can be found in the LICENSE file
19+
* in the root directory of this software component.
20+
* If no LICENSE file comes with this software, it is provided AS-IS.
2221
*
2322
******************************************************************************
2423
*/
@@ -45,11 +44,11 @@
4544
/**
4645
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
4746
*/
48-
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
49-
#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
50-
#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
51-
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
52-
#define __FPU_PRESENT 1 /*!< FPU present */
47+
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
48+
#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
49+
#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
50+
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
51+
#define __FPU_PRESENT 1U /*!< FPU present */
5352

5453
/**
5554
* @}
@@ -1204,6 +1203,15 @@ typedef struct
12041203
* @{
12051204
*/
12061205

1206+
/** @addtogroup Hardware_Constant_Definition
1207+
* @{
1208+
*/
1209+
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1210+
1211+
/**
1212+
* @}
1213+
*/
1214+
12071215
/** @addtogroup Peripheral_Registers_Bits_Definition
12081216
* @{
12091217
*/
@@ -1354,7 +1362,7 @@ typedef struct
13541362

13551363
#define ADC_CFGR_ALIGN_Pos (5U)
13561364
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1357-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1365+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
13581366

13591367
#define ADC_CFGR_EXTSEL_Pos (6U)
13601368
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -15963,4 +15971,3 @@ typedef struct
1596315971
* @}
1596415972
*/
1596515973

15966-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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