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system/Drivers/CMSIS/Device/ST Expand file tree Collapse file tree 24 files changed +70
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lines changed Original file line number Diff line number Diff line change @@ -772,12 +772,10 @@ typedef struct
772772 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
773773 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
774774 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
775- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
775+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
776776 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
777777 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
778778 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
779- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
780- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
781779} SPI_TypeDef;
782780
783781
Original file line number Diff line number Diff line change @@ -739,12 +739,10 @@ typedef struct
739739 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
740740 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
741741 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
742- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
742+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
743743 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
744744 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
745745 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
746- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
747- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
748746} SPI_TypeDef;
749747
750748
Original file line number Diff line number Diff line change @@ -788,12 +788,10 @@ typedef struct
788788 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
789789 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
790790 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
791- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
791+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
792792 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
793793 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
794794 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
795- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
796- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
797795} SPI_TypeDef;
798796
799797
Original file line number Diff line number Diff line change @@ -740,12 +740,10 @@ typedef struct
740740 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
741741 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
742742 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
743- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
743+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
744744 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
745745 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
746746 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
747- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
748- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
749747} SPI_TypeDef;
750748
751749
Original file line number Diff line number Diff line change @@ -789,12 +789,10 @@ typedef struct
789789 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
790790 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
791791 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
792- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
792+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
793793 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
794794 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
795795 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
796- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
797- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
798796} SPI_TypeDef;
799797
800798
Original file line number Diff line number Diff line change @@ -811,12 +811,10 @@ typedef struct
811811 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
812812 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
813813 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
814- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
814+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
815815 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
816816 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
817817 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
818- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
819- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
820818} SPI_TypeDef;
821819
822820
Original file line number Diff line number Diff line change @@ -812,12 +812,10 @@ typedef struct
812812 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
813813 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
814814 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
815- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
815+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
816816 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
817817 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
818818 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
819- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
820- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
821819} SPI_TypeDef;
822820
823821
Original file line number Diff line number Diff line change @@ -813,12 +813,10 @@ typedef struct
813813 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
814814 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
815815 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
816- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
816+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
817817 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
818818 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
819819 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
820- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
821- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
822820} SPI_TypeDef;
823821
824822
Original file line number Diff line number Diff line change @@ -846,12 +846,10 @@ typedef struct
846846 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
847847 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
848848 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
849- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
849+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
850850 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
851851 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
852852 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
853- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
854- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
855853} SPI_TypeDef;
856854
857855
Original file line number Diff line number Diff line change @@ -847,12 +847,10 @@ typedef struct
847847 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
848848 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
849849 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
850- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
850+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
851851 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
852852 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
853853 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
854- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
855- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
856854} SPI_TypeDef;
857855
858856
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