feat: Blues CYGNET

Author: zfields

README.md

@@ -776,7 +776,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 
 | Status | Device(s) | Name | Release | Notes |
 | :----: | :-------: | ---- | :-----: | :---- |
-| :green_heart:  | STM32L4R5ZIYx | [Swan R5](https://blues.com/products/swan) | *2.1.0* |  |
+| :green_heart:  | STM32L4R5ZIYx | [Swan R5](https://blues.com/products/swan)  |  *2.1.0*  | |
+| :yellow_heart: | STM32L433CC   | [Cygnet](https://blues.com/products) | **2.8.0** | |
 
 ### [Elecgator](https://www.elecgator.com/) boards
 

boards.txt

@@ -10806,6 +10806,21 @@ Blues.menu.pnum.SWAN_R5.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
 Blues.menu.pnum.SWAN_R5.build.vid=0x30A4
 Blues.menu.pnum.SWAN_R5.build.pid=0x0002
 
+# Cygnet board
+Blues.menu.pnum.CYGNET=Cygnet
+Blues.menu.pnum.CYGNET.upload.maximum_size=262144
+Blues.menu.pnum.CYGNET.upload.maximum_data_size=65536
+Blues.menu.pnum.CYGNET.build.mcu=cortex-m4
+Blues.menu.pnum.CYGNET.build.fpu=-mfpu=fpv4-sp-d16
+Blues.menu.pnum.CYGNET.build.float-abi=-mfloat-abi=hard
+Blues.menu.pnum.CYGNET.build.board=CYGNET
+Blues.menu.pnum.CYGNET.build.series=STM32L4xx
+Blues.menu.pnum.CYGNET.build.product_line=STM32L433xx
+Blues.menu.pnum.CYGNET.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
+Blues.menu.pnum.CYGNET.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
+Blues.menu.pnum.CYGNET_L4.build.vid=0x30A4
+Blues.menu.pnum.CYGNET_L4.build.pid=0x0003
+
 # Upload menu
 Blues.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
 Blues.menu.upload_method.swdMethod.upload.protocol=0

cmake/boards_db.cmake

@@ -106100,6 +106100,88 @@ target_compile_options(SWAN_R5_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# CYGNET
+# -----------------------------------------------------------------------------
+
+set(CYGNET_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)")
+set(CYGNET_MAXSIZE 262144)
+set(CYGNET_MAXDATASIZE 65536)
+set(CYGNET_MCU cortex-m4)
+set(CYGNET_FPCONF "fpv4-sp-d16-hard")
+add_library(CYGNET INTERFACE)
+target_compile_options(CYGNET INTERFACE
+  "SHELL:-DSTM32L4xx  "
+  "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${CYGNET_MCU}
+)
+target_compile_definitions(CYGNET INTERFACE
+  "STM32L4xx"
+	"ARDUINO_CYGNET"
+	"BOARD_NAME=\"CYGNET\""
+	"BOARD_ID=CYGNET"
+	"VARIANT_H=\"variant_CYGNET.h\""
+)
+target_include_directories(CYGNET INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
+  ${CYGNET_VARIANT_PATH}
+)
+
+target_link_options(CYGNET INTERFACE
+  "LINKER:--default-script=${CYGNET_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=262144"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=65536"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${CYGNET_MCU}
+)
+
+add_library(CYGNET_serial_disabled INTERFACE)
+target_compile_options(CYGNET_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(CYGNET_serial_generic INTERFACE)
+target_compile_options(CYGNET_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(CYGNET_serial_none INTERFACE)
+target_compile_options(CYGNET_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(CYGNET_usb_CDC INTERFACE)
+target_compile_options(CYGNET_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(CYGNET_usb_CDCgen INTERFACE)
+target_compile_options(CYGNET_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(CYGNET_usb_HID INTERFACE)
+target_compile_options(CYGNET_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(CYGNET_usb_none INTERFACE)
+target_compile_options(CYGNET_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(CYGNET_xusb_FS INTERFACE)
+target_compile_options(CYGNET_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(CYGNET_xusb_HS INTERFACE)
+target_compile_options(CYGNET_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(CYGNET_xusb_HSFS INTERFACE)
+target_compile_options(CYGNET_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # THUNDERPACK_F411
 # -----------------------------------------------------------------------------
 

tools/platformio/boards_remap.json

@@ -32,6 +32,7 @@
     "waveshare_open103z": "GENERIC_F103ZEHX",
     "bw_swan_r5": "SWAN_R5",
     "blues_swan_r5": "SWAN_R5",
+    "blues_cygnet": "CYGNET",
     "disco_b_g431b_esc1": "B_G431B_ESC1",
     "disco_b_u585i_iot02a": "B_U585I_IOT02A",
     "nucleo_wl55jc": "NUCLEO_WL55JC1"

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/CMakeLists.txt

@@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
 add_library(variant_bin STATIC EXCLUDE_FROM_ALL
   generic_clock.c
   PeripheralPins.c
+  PeripheralPins_CYGNET.c
   variant_generic.cpp
+  variant_CYGNET.cpp
 )
 target_link_libraries(variant_bin PUBLIC variant_usage)