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system(U5) update STM32U5xx HAL Drivers to v1.2.0
Included in STM32CubeU5 FW v1.2.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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‎system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 412 additions & 66 deletions
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‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h‎

Lines changed: 94 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -200,12 +200,12 @@ extern HAL_TickFreqTypeDef uwTickFreq;
200200

201201
/** @brief OTG HS PHY reference clock frequency selection
202202
*/
203-
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (0x00000003U) /*!< OTG_HS PHY reference clock frequency 16Mhz */
204-
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 (0x00000008U) /*!< OTG_HS PHY reference clock frequency 19.2Mhz */
205-
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (0x00000009U) /*!< OTG_HS PHY reference clock frequency 20Mhz */
206-
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (0x0000000AU) /*!< OTG_HS PHY reference clock frequency 24Mhz */
207-
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (0x0000000EU) /*!< OTG_HS PHY reference clock frequency 26Mhz */
208-
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (0x0000000BU) /*!< OTG_HS PHY reference clock frequency 32Mhz */
203+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */
204+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */
205+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */
206+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */
207+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */
208+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */
209209
/**
210210
* @}
211211
*/
@@ -217,8 +217,8 @@ extern HAL_TickFreqTypeDef uwTickFreq;
217217
/** @brief OTG HS PHY Power Down config
218218
*/
219219

220-
#define SYSCFG_OTG_HS_PHY_POWER_ON (0x00000000U) /*!< PHY state machine, bias and OTG PHY PLL remain powered */
221-
#define SYSCFG_OTG_HS_PHY_POWER_DOWN (0x00000001U) /*!< PHY state machine, bias and OTG PHY PLL are powered down */
220+
#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */
221+
#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */
222222

223223
/**
224224
* @}
@@ -228,8 +228,45 @@ extern HAL_TickFreqTypeDef uwTickFreq;
228228
* @{
229229
*/
230230

231-
#define SYSCFG_OTG_HS_PHY_UNDERRESET (0x00000000U) /*!< PHY under reset*/
232-
#define SYSCFG_OTG_HS_PHY_ENABLE (0x00000001U) /*!< PHY enabled */
231+
#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */
232+
#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */
233+
234+
/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current
235+
* @{
236+
*/
237+
238+
/** @brief High-speed (HS) transmitter preemphasis current control
239+
*/
240+
#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */
241+
#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */
242+
#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */
243+
#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */
244+
245+
/**
246+
* @}
247+
*/
248+
249+
/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold
250+
* @{
251+
*/
252+
253+
/** @brief Squelch threshold adjustment
254+
*/
255+
#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */
256+
#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */
257+
258+
/**
259+
* @}
260+
*/
261+
262+
/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold
263+
* @{
264+
*/
265+
266+
/** @brief Disconnect threshold adjustment
267+
*/
268+
#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */
269+
#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */
233270

234271
/**
235272
* @}
@@ -302,6 +339,16 @@ extern HAL_TickFreqTypeDef uwTickFreq;
302339
#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
303340
#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
304341

342+
#if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP)
343+
#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP)
344+
#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP)
345+
#endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */
346+
347+
#if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP)
348+
#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP)
349+
#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP)
350+
#endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */
351+
305352
#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
306353
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
307354
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
@@ -596,28 +643,31 @@ extern HAL_TickFreqTypeDef uwTickFreq;
596643
#endif /* __ARM_FEATURE_CMSE */
597644

598645
#ifdef SYSCFG_OTGHSPHYCR_EN
599-
#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) ((((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_1) == \
600-
SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \
601-
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_2) == \
602-
SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \
603-
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_3) == \
604-
SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \
605-
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_4) == \
606-
SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \
607-
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_5) == \
608-
SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \
609-
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_6) == \
610-
SYSCFG_OTG_HS_PHY_CLK_SELECT_6))
611-
612-
#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) ((((__VALUE__) & SYSCFG_OTG_HS_PHY_POWER_DOWN) == \
613-
SYSCFG_OTG_HS_PHY_POWER_DOWN) || \
614-
(((__VALUE__) & SYSCFG_OTG_HS_PHY_POWER_ON) == \
615-
SYSCFG_OTG_HS_PHY_POWER_ON))
616-
617-
#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) ((((__VALUE__) & SYSCFG_OTG_HS_PHY_UNDERRESET) == \
618-
SYSCFG_OTG_HS_PHY_UNDERRESET) || \
619-
(((__VALUE__) & SYSCFG_OTG_HS_PHY_ENABLE) == SYSCFG_OTG_HS_PHY_ENABLE))
646+
#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \
647+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \
648+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \
649+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \
650+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \
651+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6))
652+
653+
#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \
654+
((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON))
655+
656+
#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \
657+
((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE))
658+
659+
#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \
660+
((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT))
661+
662+
#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \
663+
((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT))
664+
665+
#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \
666+
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \
667+
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \
668+
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X))
620669
#endif /* SYSCFG_OTGHSPHYCR_EN */
670+
621671
/**
622672
* @}
623673
*/
@@ -668,6 +718,9 @@ void HAL_ResumeTick(void);
668718
uint32_t HAL_GetHalVersion(void);
669719
uint32_t HAL_GetREVID(void);
670720
uint32_t HAL_GetDEVID(void);
721+
uint32_t HAL_GetUIDw0(void);
722+
uint32_t HAL_GetUIDw1(void);
723+
uint32_t HAL_GetUIDw2(void);
671724

672725
/**
673726
* @}
@@ -700,13 +753,17 @@ void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
700753
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
701754
void HAL_SYSCFG_DisableVREFBUF(void);
702755
#ifdef SYSCFG_OTGHSPHYCR_EN
703-
void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection);
756+
void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection);
704757
void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig);
705758
void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig);
759+
void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold);
760+
void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold);
761+
void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent);
706762
#endif /* SYSCFG_OTGHSPHYCR_EN */
707763
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
708764
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
709-
765+
void HAL_SYSCFG_EnableSRAMCached(void);
766+
void HAL_SYSCFG_DisableSRAMCached(void);
710767
void HAL_SYSCFG_EnableVddCompensationCell(void);
711768
void HAL_SYSCFG_EnableVddIO2CompensationCell(void);
712769
#if defined(SYSCFG_CCCSR_EN3)
@@ -761,6 +818,10 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri
761818
* @}
762819
*/
763820

821+
/**
822+
* @}
823+
*/
824+
764825
#ifdef __cplusplus
765826
}
766827
#endif

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