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add variant board.txt
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‎boards.txt‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5097,6 +5097,14 @@ GenWL.menu.pnum.GENERIC_WL55JCIX.build.board=GENERIC_WL55JCIX
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GenWL.menu.pnum.GENERIC_WL55JCIX.build.product_line=STM32WL55xx
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GenWL.menu.pnum.GENERIC_WL55JCIX.build.variant=STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I
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# Generic node TTN
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GenWL.menu.pnum.GENERIC_NODE=Generic Node TTN
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GenWL.menu.pnum.GENERIC_NODE.upload.maximum_size=262144
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GenWL.menu.pnum.GENERIC_NODE.upload.maximum_data_size=65536
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GenWL.menu.pnum.GENERIC_NODE.build.board=GENERIC_NODE
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GenWL.menu.pnum.GENERIC_NODE.build.product_line=STM32WL55xx
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GenWL.menu.pnum.GENERIC_NODE.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U
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# Generic WLE4J8Ix
51015109
GenWL.menu.pnum.GENERIC_WLE4J8IX=Generic WLE4J8Ix
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GenWL.menu.pnum.GENERIC_WLE4J8IX.upload.maximum_size=65536

‎variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/ldscript.ld‎

Lines changed: 188 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,188 @@
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/** Copyright © 2021 The Things Industries B.V.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
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_Min_Heap_Size = 0x400; /* required amount of heap */
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_Min_Stack_Size = 0x800; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* Flash memory dedicated to CM4 */
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RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 dedicated to CM4 */
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RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 dedicated to CM4 */
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}
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/* Sections */
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SECTIONS
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{
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/* The startup code into "ROM" Rom type memory */
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.isr_vector :
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{
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. = ALIGN(8);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(8);
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} >ROM
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/* The program code and other data into "ROM" Rom type memory */
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.text :
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{
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. = ALIGN(8);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(8);
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_etext = .; /* define a global symbols at end of code */
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} >ROM
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/* Constant data into "ROM" Rom type memory */
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.rodata :
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{
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. = ALIGN(8);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(8);
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} >ROM
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.ARM.extab : {
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. = ALIGN(8);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(8);
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} >ROM
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.ARM : {
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. = ALIGN(8);
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__exidx_start = .;
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*(.ARM.exidx*)
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__exidx_end = .;
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. = ALIGN(8);
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} >ROM
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.preinit_array :
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{
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. = ALIGN(8);
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(8);
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} >ROM
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.init_array :
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{
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. = ALIGN(8);
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array*))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(8);
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} >ROM
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.fini_array :
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{
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. = ALIGN(8);
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT(.fini_array.*)))
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KEEP (*(.fini_array*))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(8);
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} >ROM
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/* Used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections into "SRAM1" Ram type memory */
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.data :
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{
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. = ALIGN(8);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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. = ALIGN(8);
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_edata = .; /* define a global symbol at data end */
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} >RAM1 AT> ROM
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/* Uninitialized data section into "SRAM1" Ram type memory */
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. = ALIGN(8);
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.bss :
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{
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/* This is used by the startup in order to initialize the .bss section */
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_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(8);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM1
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/* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
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. = ALIGN(8);
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RAM1_region :
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{
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_sRAM1_region = .; /* define a global symbol at section start */
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*(.RAM1_region)
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. = ALIGN(8);
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_eRAM1_region = .; /* define a global symbol at section end */
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} >RAM1
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/* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
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. = ALIGN(8);
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RAM2_region :
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{
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_sRAM2_region = .; /* define a global symbol at section start */
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*(.RAM2_region)
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. = ALIGN(8);
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_eRAM2_region = .; /* define a global symbol at section end */
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} >RAM2
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/* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
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._user_heap_stack :
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{
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. = ALIGN(8);
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PROVIDE ( end = . );
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PROVIDE ( _end = . );
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(8);
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__RAM_segment_used_end__ = .;
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} >RAM1
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/* Remove information from the compiler libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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}

‎variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_GENERIC_NODE.cpp‎

Lines changed: 80 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -15,42 +15,90 @@
1515

1616
// Digital PinName array
1717
const PinName digitalPin[] = {
18-
PB_3, // D0/USR_BTN/SWO/RTS
19-
PA_15, // D1/BUZZER
20-
PA_2, // D2/TX
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PA_3, // D3/RX
22-
PA_11, // D4/SDA2/A1
23-
PA_12, // D5/SCL2/A2
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PA_13, // D6/A3/SWDIO
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PA_14, // D7/A4/SWCLK
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PA_0, // D8/FE_CTRL1
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PA_1, // D9/FE_CTRL2
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PA_4, // D10/CS1 FLASH
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PA_5, // D11/SCK1
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PA_6, // D12/MISO
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PA_7, // D13/MOSI
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PA_8, // D14/ACCEL_INT2
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PA_9, // D15/SCL1
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PA_10, // D16/SDA1
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PB_0, // D17/VDD_TCX0
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PB_2, // D18/VABAT_ADC/A0
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PB_4, // D19/VBAT_READ_EN
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PB_5, // D20/LED_RED
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PB_6, // D21/LED_GREEN
40-
PB_7, // D22/LED_BLUE
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PB_8, // D23/FE_CTRL3
42-
PB_12, // D24/LS2_FLASH_EN
43-
PC_13, // D25/LS1_SENSORS_EN
44-
PH_3 // D26/BOOT0
18+
PB_3, // D0/USR_BTN/SWO/RTS
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PA_15, // D1/BUZZER
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PA_2, // D2/TX
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PA_3, // D3/RX
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PA_11, // D4/SDA2/A1
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PA_12, // D5/SCL2/A2
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PA_13, // D6/A3/SWDIO
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PA_14, // D7/A4/SWCLK
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PA_0, // D8/FE_CTRL1
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PA_1, // D9/FE_CTRL2
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PA_4, // D10/CS1 FLASH
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PA_5, // D11/SCK1
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PA_6, // D12/MISO
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PA_7, // D13/MOSI
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PA_8, // D14/ACCEL_INT2
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PA_9, // D15/SCL1
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PA_10, // D16/SDA1
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PB_0, // D17/VDD_TCX0
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PB_2, // D18/VABAT_ADC/A0
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PB_4, // D19/VBAT_READ_EN
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PB_5, // D20/LED_RED
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PB_6, // D21/LED_GREEN
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PB_7, // D22/LED_BLUE
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PB_8, // D23/FE_CTRL3
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PB_12, // D24/LS2_FLASH_EN
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PC_13, // D25/LS1_SENSORS_EN
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PH_3 // D26/BOOT0
4545
};
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4747
// Analog (Ax) pin number array
4848
const uint32_t analogInputPin[] = {
49-
18, // A0, PB2
50-
4, // A1, PA11
51-
5, // A2, PA12
52-
6, // A3, PA13
53-
7, // A4, PA14
49+
18, // A0, PB2
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4, // A1, PA11
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5, // A2, PA12
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6, // A3, PA13
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7, // A4, PA14
5454
};
5555

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// ----------------------------------------------------------------------------
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief System Clock Configuration
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* @param None
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* @retval None
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*/
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WEAK void SystemClock_Config(void)
68+
{
69+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
70+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
71+
72+
/** Configure the main internal regulator output voltage
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*/
74+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
75+
/** Initializes the CPU, AHB and APB busses clocks
76+
*/
77+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
78+
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
79+
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
80+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
82+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
83+
{
84+
Error_Handler();
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}
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/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
87+
*/
88+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3 | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
89+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
90+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
91+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
93+
RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
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95+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
96+
{
97+
Error_Handler();
98+
}
99+
}
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101+
#ifdef __cplusplus
102+
}
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#endif
56104
#endif /* ARDUINO_GENERIC_* */

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