Skip to content

Commit c91b6ab

Browse files
fpistmfpistm
committed
L1: Update the system source file
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 5d7daf2 commit c91b6ab

File tree

1 file changed

+92
-71
lines changed

1 file changed

+92
-71
lines changed

‎system/STM32L1xx/system_stm32l1xx.c‎

Lines changed: 92 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -3,21 +3,21 @@
33
* @file system_stm32l1xx.c
44
* @author MCD Application Team
55
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6-
*
7-
* This file provides two functions and one global variable to be called from
6+
*
7+
* This file provides two functions and one global variable to be called from
88
* user application:
9-
* - SystemInit(): This function is called at startup just after reset and
9+
* - SystemInit(): This function is called at startup just after reset and
1010
* before branch to main program. This call is made inside
1111
* the "startup_stm32l1xx.s" file.
12-
*
12+
*
1313
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14-
* by the user application to setup the SysTick
14+
* by the user application to setup the SysTick
1515
* timer or configure other parameters.
16-
*
16+
*
1717
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
1818
* be called whenever the core clock is changed
19-
* during program execution.
20-
*
19+
* during program execution.
20+
*
2121
******************************************************************************
2222
* @attention
2323
*
@@ -38,8 +38,8 @@
3838

3939
/** @addtogroup stm32l1xx_system
4040
* @{
41-
*/
42-
41+
*/
42+
4343
/** @addtogroup STM32L1xx_System_Private_Includes
4444
* @{
4545
*/
@@ -65,14 +65,36 @@
6565
/*!< Uncomment the following line if you need to use external SRAM mounted
6666
on STM32L152D_EVAL board as data memory */
6767
/* #define DATA_IN_ExtSRAM */
68-
69-
/*!< Uncomment the following line if you need to relocate your vector Table in
70-
Internal SRAM. */
71-
/* #define VECT_TAB_SRAM */
68+
69+
7270
#ifndef VECT_TAB_OFFSET
73-
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
74-
This value must be a multiple of 0x200. */
71+
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
72+
This value must be a multiple of 0x200. */
73+
#else
74+
#define USER_VECT_TAB_ADDRESS
7575
#endif
76+
77+
/* Note: Following vector table addresses must be defined in line with linker
78+
configuration. */
79+
/*!< Uncomment the following line if you need to relocate the vector table
80+
anywhere in Flash or Sram, else the vector table is kept at the automatic
81+
remap of boot address selected */
82+
/* #define USER_VECT_TAB_ADDRESS */
83+
84+
#if defined(USER_VECT_TAB_ADDRESS)
85+
/*!< Uncomment the following line if you need to relocate your vector Table
86+
in Sram else user remap will be done in Flash. */
87+
/* #define VECT_TAB_SRAM */
88+
#if defined(VECT_TAB_SRAM)
89+
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
90+
This value must be a multiple of 0x200. */
91+
#else
92+
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
93+
This value must be a multiple of 0x200. */
94+
#endif /* VECT_TAB_SRAM */
95+
#endif /* USER_VECT_TAB_ADDRESS */
96+
97+
/******************************************************************************/
7698
/**
7799
* @}
78100
*/
@@ -111,7 +133,7 @@ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
111133

112134
#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
113135
#ifdef DATA_IN_ExtSRAM
114-
static void SystemInit_ExtMemCtl(void);
136+
static void SystemInit_ExtMemCtl(void);
115137
#endif /* DATA_IN_ExtSRAM */
116138
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
117139

@@ -125,7 +147,7 @@ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
125147

126148
/**
127149
* @brief Setup the microcontroller system.
128-
* Initialize the Embedded Flash Interface, the PLL and update the
150+
* Initialize the Embedded Flash Interface, the PLL and update the
129151
* SystemCoreClock variable.
130152
* @param None
131153
* @retval None
@@ -151,49 +173,48 @@ void SystemInit (void)
151173
RCC->CIR = 0x00000000;
152174

153175
#ifdef DATA_IN_ExtSRAM
154-
SystemInit_ExtMemCtl();
176+
SystemInit_ExtMemCtl();
155177
#endif /* DATA_IN_ExtSRAM */
156-
157-
#ifdef VECT_TAB_SRAM
158-
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
159-
#else
160-
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
161-
#endif
178+
179+
/* Configure the Vector Table location -------------------------------------*/
180+
#if defined(USER_VECT_TAB_ADDRESS)
181+
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH or SRAM. */
182+
#endif /* USER_VECT_TAB_ADDRESS */
162183
}
163184

164185
/**
165186
* @brief Update SystemCoreClock according to Clock Register Values
166187
* The SystemCoreClock variable contains the core clock (HCLK), it can
167188
* be used by the user application to setup the SysTick timer or configure
168189
* other parameters.
169-
*
190+
*
170191
* @note Each time the core clock (HCLK) changes, this function must be called
171192
* to update SystemCoreClock variable value. Otherwise, any configuration
172-
* based on this variable will be incorrect.
173-
*
174-
* @note - The system frequency computed by this function is not the real
175-
* frequency in the chip. It is calculated based on the predefined
193+
* based on this variable will be incorrect.
194+
*
195+
* @note - The system frequency computed by this function is not the real
196+
* frequency in the chip. It is calculated based on the predefined
176197
* constant and the selected clock source:
177-
*
178-
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
198+
*
199+
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
179200
* value as defined by the MSI range.
180-
*
201+
*
181202
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
182-
*
203+
*
183204
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
184-
*
205+
*
185206
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
186207
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
187-
*
208+
*
188209
* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
189210
* 16 MHz) but the real value may vary depending on the variations
190-
* in voltage and temperature.
191-
*
211+
* in voltage and temperature.
212+
*
192213
* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
193214
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
194215
* frequency of the crystal used. Otherwise, this function may
195216
* have wrong result.
196-
*
217+
*
197218
* - The result of this function could be not correct when using fractional
198219
* value for HSE crystal.
199220
* @param None
@@ -205,7 +226,7 @@ void SystemCoreClockUpdate (void)
205226

206227
/* Get SYSCLK source -------------------------------------------------------*/
207228
tmp = RCC->CFGR & RCC_CFGR_SWS;
208-
229+
209230
switch (tmp)
210231
{
211232
case 0x00: /* MSI used as system clock */
@@ -224,7 +245,7 @@ void SystemCoreClockUpdate (void)
224245
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
225246
pllmul = PLLMulTable[(pllmul >> 18)];
226247
plldiv = (plldiv >> 22) + 1;
227-
248+
228249
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
229250

230251
if (pllsource == 0x00)
@@ -266,21 +287,21 @@ void SystemInit_ExtMemCtl(void)
266287

267288
/* Flash 1 wait state */
268289
FLASH->ACR |= FLASH_ACR_LATENCY;
269-
290+
270291
/* Power enable */
271292
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
272-
293+
273294
/* Delay after an RCC peripheral clock enabling */
274295
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
275296

276297
/* Select the Voltage Range 1 (1.8 V) */
277298
PWR->CR = PWR_CR_VOS_0;
278-
299+
279300
/* Wait Until the Voltage Regulator is ready */
280301
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
281302
{
282303
}
283-
304+
284305
/*-- GPIOs Configuration -----------------------------------------------------*/
285306
/*
286307
+-------------------+--------------------+------------------+------------------+
@@ -294,76 +315,76 @@ void SystemInit_ExtMemCtl(void)
294315
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
295316
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
296317
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
297-
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
298-
| PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
318+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
319+
| PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
299320
| PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
300-
| PD15 <-> FSMC_D1 |--------------------+
321+
| PD15 <-> FSMC_D1 |--------------------+
301322
+-------------------+
302323
*/
303324

304325
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
305326
RCC->AHBENR = 0x000080D8;
306-
327+
307328
/* Delay after an RCC peripheral clock enabling */
308329
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
309-
330+
310331
/* Connect PDx pins to FSMC Alternate function */
311332
GPIOD->AFR[0] = 0x00CC00CC;
312333
GPIOD->AFR[1] = 0xCCCCCCCC;
313-
/* Configure PDx pins in Alternate function mode */
334+
/* Configure PDx pins in Alternate function mode */
314335
GPIOD->MODER = 0xAAAA0A0A;
315-
/* Configure PDx pins speed to 40 MHz */
336+
/* Configure PDx pins speed to 40 MHz */
316337
GPIOD->OSPEEDR = 0xFFFF0F0F;
317-
/* Configure PDx pins Output type to push-pull */
338+
/* Configure PDx pins Output type to push-pull */
318339
GPIOD->OTYPER = 0x00000000;
319-
/* No pull-up, pull-down for PDx pins */
340+
/* No pull-up, pull-down for PDx pins */
320341
GPIOD->PUPDR = 0x00000000;
321342

322343
/* Connect PEx pins to FSMC Alternate function */
323344
GPIOE->AFR[0] = 0xC00000CC;
324345
GPIOE->AFR[1] = 0xCCCCCCCC;
325-
/* Configure PEx pins in Alternate function mode */
346+
/* Configure PEx pins in Alternate function mode */
326347
GPIOE->MODER = 0xAAAA800A;
327-
/* Configure PEx pins speed to 40 MHz */
348+
/* Configure PEx pins speed to 40 MHz */
328349
GPIOE->OSPEEDR = 0xFFFFC00F;
329-
/* Configure PEx pins Output type to push-pull */
350+
/* Configure PEx pins Output type to push-pull */
330351
GPIOE->OTYPER = 0x00000000;
331-
/* No pull-up, pull-down for PEx pins */
352+
/* No pull-up, pull-down for PEx pins */
332353
GPIOE->PUPDR = 0x00000000;
333354

334355
/* Connect PFx pins to FSMC Alternate function */
335356
GPIOF->AFR[0] = 0x00CCCCCC;
336357
GPIOF->AFR[1] = 0xCCCC0000;
337-
/* Configure PFx pins in Alternate function mode */
358+
/* Configure PFx pins in Alternate function mode */
338359
GPIOF->MODER = 0xAA000AAA;
339-
/* Configure PFx pins speed to 40 MHz */
360+
/* Configure PFx pins speed to 40 MHz */
340361
GPIOF->OSPEEDR = 0xFF000FFF;
341-
/* Configure PFx pins Output type to push-pull */
362+
/* Configure PFx pins Output type to push-pull */
342363
GPIOF->OTYPER = 0x00000000;
343-
/* No pull-up, pull-down for PFx pins */
364+
/* No pull-up, pull-down for PFx pins */
344365
GPIOF->PUPDR = 0x00000000;
345366

346367
/* Connect PGx pins to FSMC Alternate function */
347368
GPIOG->AFR[0] = 0x00CCCCCC;
348369
GPIOG->AFR[1] = 0x00000C00;
349-
/* Configure PGx pins in Alternate function mode */
370+
/* Configure PGx pins in Alternate function mode */
350371
GPIOG->MODER = 0x00200AAA;
351-
/* Configure PGx pins speed to 40 MHz */
372+
/* Configure PGx pins speed to 40 MHz */
352373
GPIOG->OSPEEDR = 0x00300FFF;
353-
/* Configure PGx pins Output type to push-pull */
374+
/* Configure PGx pins Output type to push-pull */
354375
GPIOG->OTYPER = 0x00000000;
355-
/* No pull-up, pull-down for PGx pins */
376+
/* No pull-up, pull-down for PGx pins */
356377
GPIOG->PUPDR = 0x00000000;
357-
378+
358379
/*-- FSMC Configuration ------------------------------------------------------*/
359380
/* Enable the FSMC interface clock */
360381
RCC->AHBENR = 0x400080D8;
361382

362383
/* Delay after an RCC peripheral clock enabling */
363384
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
364-
385+
365386
(void)(tmpreg);
366-
387+
367388
/* Configure and enable Bank1_SRAM3 */
368389
FSMC_Bank1->BTCR[4] = 0x00001011;
369390
FSMC_Bank1->BTCR[5] = 0x00000300;
@@ -395,11 +416,11 @@ void SystemInit_ExtMemCtl(void)
395416
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
396417
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
397418
398-
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
419+
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
399420
400421
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
401422
*/
402-
423+
403424
}
404425
#endif /* DATA_IN_ExtSRAM */
405426
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */

0 commit comments

Comments
 (0)