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Review variant NUCLEO_F401RE
Align analog pins definition Add some clean Signed-off-by: Frederic.Pillon <frederic.pillon@st.com>
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-56
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4 files changed

+58
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‎variants/NUCLEO_F401RE/PeripheralPins.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ const PinMap PinMap_ADC[] = {
4444
// {PA2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
4545
// {PA3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
4646
{PA4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
47-
{PA5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
47+
// {PA5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - LED1
4848
{PA6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
4949
{PA7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
5050
{PB0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8

‎variants/NUCLEO_F401RE/stm32f4xx_hal_conf.h‎

Lines changed: 45 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -104,11 +104,11 @@
104104
* (when HSE is used as system clock source, directly or through the PLL).
105105
*/
106106
#if !defined (HSE_VALUE)
107-
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
107+
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
108108
#endif /* HSE_VALUE */
109109

110110
#if !defined (HSE_STARTUP_TIMEOUT)
111-
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
111+
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
112112
#endif /* HSE_STARTUP_TIMEOUT */
113113

114114
/**
@@ -117,26 +117,26 @@
117117
* (when HSI is used as system clock source, directly or through the PLL).
118118
*/
119119
#if !defined (HSI_VALUE)
120-
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
120+
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */
121121
#endif /* HSI_VALUE */
122122

123123
/**
124124
* @brief Internal Low Speed oscillator (LSI) value.
125125
*/
126126
#if !defined (LSI_VALUE)
127-
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
127+
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
128128
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
129129
The real value may vary depending on the variations
130130
in voltage and temperature.*/
131131
/**
132132
* @brief External Low Speed oscillator (LSE) value.
133133
*/
134134
#if !defined (LSE_VALUE)
135-
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
135+
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
136136
#endif /* LSE_VALUE */
137137

138138
#if !defined (LSE_STARTUP_TIMEOUT)
139-
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
139+
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
140140
#endif /* LSE_STARTUP_TIMEOUT */
141141

142142
/**
@@ -145,7 +145,7 @@
145145
* frequency, this source is inserted directly through I2S_CKIN pad.
146146
*/
147147
#if !defined (EXTERNAL_CLOCK_VALUE)
148-
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
148+
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
149149
#endif /* EXTERNAL_CLOCK_VALUE */
150150

151151
/* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -155,8 +155,8 @@
155155
/**
156156
* @brief This is the HAL system configuration section
157157
*/
158-
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
159-
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
158+
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
159+
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
160160
#define USE_RTOS 0U
161161
#define PREFETCH_ENABLE 1U
162162
#define INSTRUCTION_CACHE_ENABLE 1U
@@ -184,46 +184,56 @@
184184
/* Definition of the Ethernet driver buffers size and count */
185185
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
186186
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
187-
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
188-
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
187+
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
188+
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
189189

190190
/* Section 2: PHY configuration section */
191191

192-
/* DP83848_PHY_ADDRESS Address*/
192+
/* DP83848 PHY Address*/
193193
#define DP83848_PHY_ADDRESS 0x01U
194194
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
195-
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
195+
#define PHY_RESET_DELAY 0x000000FFU
196196
/* PHY Configuration delay */
197-
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
197+
#define PHY_CONFIG_DELAY 0x00000FFFU
198198

199-
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
200-
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
199+
#define PHY_READ_TO 0x0000FFFFU
200+
#define PHY_WRITE_TO 0x0000FFFFU
201201

202202
/* Section 3: Common PHY Registers */
203203

204-
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
205-
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
204+
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
205+
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
206206

207-
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
208-
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
209-
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
210-
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
211-
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
212-
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
213-
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
214-
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
215-
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
216-
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
217-
218-
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
219-
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
220-
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
207+
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
208+
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
209+
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
210+
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
211+
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
212+
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
213+
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
214+
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
215+
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
216+
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
217+
218+
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
219+
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
220+
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
221221

222222
/* Section 4: Extended PHY Registers */
223-
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
224223

225-
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
226-
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
224+
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
225+
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
226+
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
227+
228+
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
229+
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
230+
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
231+
232+
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
233+
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
234+
235+
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
236+
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
227237

228238
/* ################## SPI peripheral configuration ########################## */
229239

‎variants/NUCLEO_F401RE/variant.cpp‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,14 @@ const PinName digitalPin[] = {
8181
PB0, //D49/A3
8282
PC1, //D50/A4
8383
PC0, //D51/A5
84+
// Duplicated pins in order to be aligned with PinMap_ADC
85+
PA7, //D52/A6 = D11
86+
PA6, //D53/A7 = D12
87+
PC2, //D54/A8 = D28
88+
PC3, //D55/A9 = D29
89+
PC5, //D56/A10 = D35
90+
PB1, //D57/A11 = D41
91+
PC4 //D58/A12 = D45
8492
};
8593

8694
#ifdef __cplusplus
@@ -195,4 +203,4 @@ WEAK void SystemClock_Config(void)
195203

196204
#ifdef __cplusplus
197205
}
198-
#endif
206+
#endif

‎variants/NUCLEO_F401RE/variant.h‎

Lines changed: 3 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -19,16 +19,6 @@
1919
#ifndef _VARIANT_ARDUINO_STM32_
2020
#define _VARIANT_ARDUINO_STM32_
2121

22-
/*----------------------------------------------------------------------------
23-
* Definitions
24-
*----------------------------------------------------------------------------*/
25-
26-
/** Frequency of the board main oscillator */
27-
//#define VARIANT_MAINOSC 12000000
28-
29-
/** Master clock frequency */
30-
//#define VARIANT_MCK 84000000
31-
3222
/*----------------------------------------------------------------------------
3323
* Headers
3424
*----------------------------------------------------------------------------*/
@@ -39,13 +29,6 @@
3929
extern "C"{
4030
#endif // __cplusplus
4131

42-
/**
43-
* Libc porting layers
44-
*/
45-
//#if defined ( __GNUC__ ) /* GCC CS3 */
46-
//# include <syscalls.h> /** RedHat Newlib minimal stub */
47-
//#endif*/
48-
4932
/*----------------------------------------------------------------------------
5033
* Pins
5134
*----------------------------------------------------------------------------*/
@@ -59,13 +42,14 @@ enum {
5942
D20, D21, D22, D23, D24, D25, D26, D27, D28, D29,
6043
D30, D31, D32, D33, D34, D35, D36, D37, D38, D39,
6144
D40, D41, D42, D43, D44, D45, D46, D47, D48, D49,
62-
D50, D51,
45+
D50, D51, D52, D53, D54, D55, D56, D57, D58,
6346
DEND
6447
};
6548

6649
enum {
6750
A_START_AFTER = D45,
68-
A0, A1, A2, A3, A4, A5,
51+
A0, A1, A2, A3, A4, A5, A6, A7, A8, A9,
52+
A10, A11, A12,
6953
AEND
7054
};
7155

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