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2 | 2 | ****************************************************************************** |
3 | 3 | * @file stm32f1xx_hal_conf.h |
4 | 4 | * @author MCD Application Team |
5 | | - * @version V1.0.4 |
6 | | - * @date 29-April-2016 |
| 5 | + * @version V1.1.1 |
| 6 | + * @date 12-May-2017 |
7 | 7 | * @brief HAL configuration template file. |
8 | 8 | * This file should be copied to the application folder and renamed |
9 | 9 | * to stm32f1xx_hal_conf.h. |
10 | 10 | ****************************************************************************** |
11 | 11 | * @attention |
12 | 12 | * |
13 | | - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| 13 | + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
14 | 14 | * |
15 | 15 | * Redistribution and use in source and binary forms, with or without modification, |
16 | 16 | * are permitted provided that the following conditions are met: |
|
83 | 83 | #define HAL_UART_MODULE_ENABLED |
84 | 84 | //#define HAL_USART_MODULE_ENABLED |
85 | 85 | //#define HAL_WWDG_MODULE_ENABLED |
| 86 | +#define HAL_MMC_MODULE_ENABLED |
86 | 87 |
|
87 | 88 | /* ########################## Oscillator Values adaptation ####################*/ |
88 | 89 | /** |
|
92 | 93 | */ |
93 | 94 | #if !defined (HSE_VALUE) |
94 | 95 | #if defined(USE_STM3210C_EVAL) |
95 | | - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ |
| 96 | + #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ |
96 | 97 | #else |
97 | | - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ |
| 98 | + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ |
98 | 99 | #endif |
99 | 100 | #endif /* HSE_VALUE */ |
100 | 101 |
|
101 | 102 | #if !defined (HSE_STARTUP_TIMEOUT) |
102 | | - #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ |
| 103 | + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ |
103 | 104 | #endif /* HSE_STARTUP_TIMEOUT */ |
104 | 105 |
|
105 | 106 | /** |
|
108 | 109 | * (when HSI is used as system clock source, directly or through the PLL). |
109 | 110 | */ |
110 | 111 | #if !defined (HSI_VALUE) |
111 | | - #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ |
| 112 | + #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */ |
112 | 113 | #endif /* HSI_VALUE */ |
113 | 114 |
|
| 115 | +/** |
| 116 | + * @brief Internal Low Speed oscillator (LSI) value. |
| 117 | + */ |
| 118 | +#if !defined (LSI_VALUE) |
| 119 | + #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ |
| 120 | +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz |
| 121 | + The real value may vary depending on the variations |
| 122 | + in voltage and temperature. */ |
114 | 123 | /** |
115 | 124 | * @brief External Low Speed oscillator (LSE) value. |
116 | 125 | * This value is used by the UART, RTC HAL module to compute the system frequency |
117 | 126 | */ |
118 | 127 | #if !defined (LSE_VALUE) |
119 | | - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ |
| 128 | + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ |
120 | 129 | #endif /* LSE_VALUE */ |
121 | 130 |
|
122 | | - |
123 | 131 | #if !defined (LSE_STARTUP_TIMEOUT) |
124 | | - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ |
125 | | -#endif /* HSE_STARTUP_TIMEOUT */ |
126 | | - |
| 132 | + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ |
| 133 | +#endif /* LSE_STARTUP_TIMEOUT */ |
127 | 134 |
|
128 | 135 | /* Tip: To avoid modifying this file each time you need to use different HSE, |
129 | 136 | === you can define the HSE value in your toolchain compiler preprocessor. */ |
|
132 | 139 | /** |
133 | 140 | * @brief This is the HAL system configuration section |
134 | 141 | */ |
135 | | -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ |
136 | | -#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */ |
137 | | -#define USE_RTOS 0 |
138 | | -#define PREFETCH_ENABLE 1 |
| 142 | +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ |
| 143 | +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ |
| 144 | +#define USE_RTOS 0U |
| 145 | +#define PREFETCH_ENABLE 1U |
139 | 146 |
|
140 | 147 | /* ########################## Assert Selection ############################## */ |
141 | 148 | /** |
142 | 149 | * @brief Uncomment the line below to expanse the "assert_param" macro in the |
143 | 150 | * HAL drivers code |
144 | 151 | */ |
145 | | -/*#define USE_FULL_ASSERT 1*/ |
146 | | - |
| 152 | +/* #define USE_FULL_ASSERT 1U */ |
147 | 153 |
|
148 | 154 | /* ################## Ethernet peripheral configuration ##################### */ |
149 | 155 |
|
150 | 156 | /* Section 1 : Ethernet peripheral configuration */ |
151 | 157 |
|
152 | 158 | /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ |
153 | | -#define MAC_ADDR0 2 |
154 | | -#define MAC_ADDR1 0 |
155 | | -#define MAC_ADDR2 0 |
156 | | -#define MAC_ADDR3 0 |
157 | | -#define MAC_ADDR4 0 |
158 | | -#define MAC_ADDR5 0 |
| 159 | +#define MAC_ADDR0 2U |
| 160 | +#define MAC_ADDR1 0U |
| 161 | +#define MAC_ADDR2 0U |
| 162 | +#define MAC_ADDR3 0U |
| 163 | +#define MAC_ADDR4 0U |
| 164 | +#define MAC_ADDR5 0U |
159 | 165 |
|
160 | 166 | /* Definition of the Ethernet driver buffers size and count */ |
161 | 167 | #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ |
162 | 168 | #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ |
163 | | -#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ |
164 | | -#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ |
| 169 | +#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */ |
| 170 | +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ |
165 | 171 |
|
166 | 172 | /* Section 2: PHY configuration section */ |
167 | 173 |
|
168 | 174 | /* DP83848 PHY Address*/ |
169 | | -#define DP83848_PHY_ADDRESS 0x01 |
| 175 | +#define DP83848_PHY_ADDRESS 0x01U |
170 | 176 | /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ |
171 | | -#define PHY_RESET_DELAY ((uint32_t)0x000000FF) |
| 177 | +#define PHY_RESET_DELAY 0x000000FFU |
172 | 178 | /* PHY Configuration delay */ |
173 | | -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) |
| 179 | +#define PHY_CONFIG_DELAY 0x00000FFFU |
174 | 180 |
|
175 | | -#define PHY_READ_TO ((uint32_t)0x0000FFFF) |
176 | | -#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) |
| 181 | +#define PHY_READ_TO 0x0000FFFFU |
| 182 | +#define PHY_WRITE_TO 0x0000FFFFU |
177 | 183 |
|
178 | 184 | /* Section 3: Common PHY Registers */ |
179 | 185 |
|
180 | | -#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ |
181 | | -#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ |
| 186 | +#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ |
| 187 | +#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ |
182 | 188 |
|
183 | 189 | #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ |
184 | 190 | #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ |
|
197 | 203 |
|
198 | 204 | /* Section 4: Extended PHY Registers */ |
199 | 205 |
|
200 | | -#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ |
201 | | -#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ |
202 | | -#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ |
| 206 | +#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ |
| 207 | +#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ |
| 208 | +#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ |
203 | 209 |
|
204 | 210 | #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ |
205 | 211 | #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ |
|
211 | 217 | #define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ |
212 | 218 | #define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ |
213 | 219 |
|
| 220 | +/* ################## SPI peripheral configuration ########################## */ |
214 | 221 |
|
| 222 | +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver |
| 223 | +* Activated: CRC code is present inside driver |
| 224 | +* Deactivated: CRC code cleaned from driver |
| 225 | +*/ |
| 226 | + |
| 227 | +#define USE_SPI_CRC 1U |
215 | 228 |
|
216 | 229 | /* Includes ------------------------------------------------------------------*/ |
217 | 230 | /** |
|
334 | 347 | #include "stm32f1xx_hal_pcd.h" |
335 | 348 | #endif /* HAL_PCD_MODULE_ENABLED */ |
336 | 349 |
|
337 | | - |
338 | 350 | #ifdef HAL_HCD_MODULE_ENABLED |
339 | 351 | #include "stm32f1xx_hal_hcd.h" |
340 | 352 | #endif /* HAL_HCD_MODULE_ENABLED */ |
341 | 353 |
|
| 354 | +#ifdef HAL_MMC_MODULE_ENABLED |
| 355 | + #include "stm32f1xx_hal_mmc.h" |
| 356 | +#endif /* HAL_MMC_MODULE_ENABLED */ |
342 | 357 |
|
343 | 358 | /* Exported macro ------------------------------------------------------------*/ |
344 | 359 | #ifdef USE_FULL_ASSERT |
|
350 | 365 | * If expr is true, it returns no value. |
351 | 366 | * @retval None |
352 | 367 | */ |
353 | | - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) |
| 368 | + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) |
354 | 369 | /* Exported functions ------------------------------------------------------- */ |
355 | 370 | void assert_failed(uint8_t* file, uint32_t line); |
356 | 371 | #else |
357 | | - #define assert_param(expr) ((void)0) |
| 372 | + #define assert_param(expr) ((void)0U) |
358 | 373 | #endif /* USE_FULL_ASSERT */ |
359 | 374 |
|
360 | 375 | #ifdef __cplusplus |
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