Allow VECT_TAB_OFFSET to be override

Signed-off-by: fpr <fabien.perroquin@wi6labs.com>

Author: fpr

system/STM32F1xx/system_stm32f1xx.c

@@ -5,19 +5,19 @@
   * @version V4.1.0
   * @date    29-April-2016
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
+  *
+  * 1.  This file provides two functions and one global variable to be called from
   *     user application:
   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
+  *                      factors, AHB/APBx prescalers and Flash settings).
+  *                      This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32f1xx_xx.s" file.
   *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
+  *                                  by the user application to setup the SysTick
   *                                  timer or configure other parameters.
-  *                                     
+  *
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
@@ -27,11 +27,11 @@
   *    configure the system clock before to branch to main program.
   *
   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
-  *    the product used), refer to "HSE_VALUE". 
+  *    the product used), refer to "HSE_VALUE".
   *    When HSE is used as system clock source, directly or through PLL, and you
   *    are using different crystal you have to adapt the HSE value to your own
   *    configuration.
-  *        
+  *
   ******************************************************************************
   * @attention
   *
@@ -68,8 +68,8 @@
 
 /** @addtogroup stm32f1xx_system
   * @{
-  */  
-  
+  */
+
 /** @addtogroup STM32F1xx_System_Private_Includes
   * @{
   */
@@ -92,7 +92,7 @@
   * @{
   */
 
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
                                                 This value can be provided and adapted by the user application. */
 #endif /* HSE_VALUE */
@@ -102,16 +102,18 @@
                                                 This value can be provided and adapted by the user application. */
 #endif /* HSI_VALUE */
 
-/*!< Uncomment the following line if you need to use external SRAM  */ 
+/*!< Uncomment the following line if you need to use external SRAM  */
 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 /* #define DATA_IN_ExtSRAM */
 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
+     Internal SRAM. */
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+#ifndef VECT_TAB_OFFSET
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
                                   This value must be a multiple of 0x200. */
+#endif
 
 
 /**
@@ -148,7 +150,7 @@ const uint8_t APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
 
 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 #ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
+  static void SystemInit_ExtMemCtl(void);
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 
@@ -162,7 +164,7 @@ const uint8_t APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
 
 /**
   * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         Initialize the Embedded Flash Interface, the PLL and update the
   *         SystemCoreClock variable.
   * @note   This function should be used only after reset.
   * @param  None
@@ -179,8 +181,8 @@ void SystemInit (void)
   RCC->CFGR &= (uint32_t)0xF8FF0000;
 #else
   RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F105xC */   
-  
+#endif /* STM32F105xC */
+
   /* Reset HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xFEF6FFFF;
 
@@ -204,55 +206,55 @@ void SystemInit (void)
   RCC->CIR = 0x009F0000;
 
   /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
+  RCC->CFGR2 = 0x00000000;
 #else
   /* Disable all interrupts and clear pending bits  */
   RCC->CIR = 0x009F0000;
 #endif /* STM32F105xC */
-    
+
 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
   #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
+    SystemInit_ExtMemCtl();
   #endif /* DATA_IN_ExtSRAM */
-#endif 
+#endif
 
 #ifdef VECT_TAB_SRAM
   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
+#endif
 }
 
 /**
   * @brief  Update SystemCoreClock variable according to Clock Register Values.
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
   *         be used by the user application to setup the SysTick timer or configure
   *         other parameters.
-  *           
+  *
   * @note   Each time the core clock (HCLK) changes, this function must be called
   *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
   *           constant and the selected clock source:
-  *             
+  *
   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
+  *
   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
   *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
+  *
   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
   *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
+  *             in voltage and temperature.
+  *
   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
   *              8 MHz or 25 MHz, depending on the product used), user has to ensure
   *              that HSE_VALUE is same as the real frequency of the crystal used.
   *              Otherwise, this function may have wrong result.
-  *                
+  *
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
   * @param  None
@@ -269,10 +271,10 @@ void SystemCoreClockUpdate (void)
 #if defined(STM32F100xB) || defined(STM32F100xE)
   uint32_t prediv1factor = 0;
 #endif /* STM32F100xB or STM32F100xE */
-    
+
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
+
   switch (tmp)
   {
     case 0x00:  /* HSI used as system clock */
@@ -286,10 +288,10 @@ void SystemCoreClockUpdate (void)
       /* Get PLL clock source and multiplication factor ----------------------*/
       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#if !defined(STM32F105xC) && !defined(STM32F107xC)      
+
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
       pllmull = ( pllmull >> 18) + 2;
-      
+
       if (pllsource == 0x00)
       {
         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
@@ -300,7 +302,7 @@ void SystemCoreClockUpdate (void)
  #if defined(STM32F100xB) || defined(STM32F100xE)
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
        /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
  #else
         /* HSE selected as PLL clock entry */
         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
@@ -315,115 +317,115 @@ void SystemCoreClockUpdate (void)
       }
 #else
       pllmull = pllmull >> 18;
-      
+
       if (pllmull != 0x0D)
       {
          pllmull += 2;
       }
       else
       { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
+        pllmull = 13 / 2;
       }
-            
+
       if (pllsource == 0x00)
       {
         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
       }
       else
       {/* PREDIV1 selected as PLL clock entry */
-        
+
         /* Get PREDIV1 clock source and division factor */
         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
+
         if (prediv1source == 0)
-        { 
+        {
           /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
         }
         else
         {/* PLL2 clock selected as PREDIV1 clock entry */
-          
+
           /* Get PREDIV2 division factor and PLL2 multiplication factor */
           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
         }
       }
-#endif /* STM32F105xC */ 
+#endif /* STM32F105xC */
       break;
 
     default:
       SystemCoreClock = HSI_VALUE;
       break;
   }
-  
+
   /* Compute HCLK clock frequency ----------------*/
   /* Get HCLK prescaler */
   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
   /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
+  SystemCoreClock >>= tmp;
 }
 
 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 /**
-  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
+  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s
   *          before jump to __main
   * @param  None
   * @retval None
-  */ 
+  */
 #ifdef DATA_IN_ExtSRAM
 /**
-  * @brief  Setup the external memory controller. 
+  * @brief  Setup the external memory controller.
   *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
   *         This function configures the external SRAM mounted on STM3210E-EVAL
   *         board (STM32 High density devices). This SRAM will be used as program
   *         data memory (including heap and stack).
   * @param  None
   * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
+  */
+void SystemInit_ExtMemCtl(void)
 {
   __IO uint32_t tmpreg;
-  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
     required, then adjust the Register Addresses */
 
   /* Enable FSMC clock */
   RCC->AHBENR = 0x00000114;
 
   /* Delay after an RCC peripheral clock enabling */
   tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
+
   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
   RCC->APB2ENR = 0x000001E0;
-  
+
   /* Delay after an RCC peripheral clock enabling */
   tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
 
   (void)(tmpreg);
-  
+
 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
 /*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NOE and NWE configuration --------------------------------*/
 /*----------------  NE3 configuration ----------------------------------------*/
 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
+
+  GPIOD->CRL = 0x44BB44BB;
   GPIOD->CRH = 0xBBBBBBBB;
 
-  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRL = 0xB44444BB;
   GPIOE->CRH = 0xBBBBBBBB;
 
-  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRL = 0x44BBBBBB;
   GPIOF->CRH = 0xBBBB4444;
 
-  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRL = 0x44BBBBBB;
   GPIOG->CRH = 0x444B4B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
+
+/*----------------  FSMC Configuration ---------------------------------------*/
 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
+
   FSMC_Bank1->BTCR[4] = 0x00001091;
   FSMC_Bank1->BTCR[5] = 0x00110212;
 }
@@ -437,8 +439,8 @@ void SystemInit_ExtMemCtl(void)
 /**
   * @}
   */
-  
+
 /**
   * @}
-  */    
+  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/