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63 | 63 | * <h2><center>© Copyright (c) 2019 STMicroelectronics. |
64 | 64 | * All rights reserved.</center></h2> |
65 | 65 | * |
66 | | - * This software component is licensed by ST under BSD 3-Clause license, |
| 66 | + * This software component is licensed by ST under Apache License, Version 2.0, |
67 | 67 | * the "License"; You may not use this file except in compliance with the |
68 | 68 | * License. You may obtain a copy of the License at: |
69 | | - * opensource.org/licenses/BSD-3-Clause |
| 69 | + * opensource.org/licenses/Apache-2.0 |
70 | 70 | * |
71 | 71 | ****************************************************************************** |
72 | 72 | */ |
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101 | 101 | * @{ |
102 | 102 | */ |
103 | 103 |
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104 | | -/*!< Uncomment the following line if you need to relocate your vector Table in |
105 | | - Internal SRAM. */ |
106 | | -/* #define VECT_TAB_SRAM */ |
107 | 104 | #ifndef VECT_TAB_OFFSET |
108 | | -#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. |
| 105 | +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
109 | 106 | This value must be a multiple of 0x200. */ |
| 107 | +#else |
| 108 | +#define USER_VECT_TAB_ADDRESS |
110 | 109 | #endif |
111 | | -#ifndef VECT_TAB_BASE_ADDRESS |
112 | | -#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base offset field. |
| 110 | + |
| 111 | +/* Note: Following vector table addresses must be defined in line with linker |
| 112 | + configuration. */ |
| 113 | +/*!< Define USER_VECT_TAB_ADDRESS if you need to relocate CPU1 CM4 and/or CPU2 |
| 114 | + CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept |
| 115 | + at address 0x00 which correspond to automatic remap of boot address selected */ |
| 116 | +#if defined(USER_VECT_TAB_ADDRESS) |
| 117 | + /*!< Define VECT_TAB_SRAM for user vector table remap in Sram else user remap |
| 118 | + will be done in Flash. */ |
| 119 | +#if defined(VECT_TAB_SRAM) |
| 120 | +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. |
| 121 | + This value must be a multiple of 0x200. */ |
| 122 | +#else |
| 123 | +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. |
113 | 124 | This value must be a multiple of 0x200. */ |
114 | 125 | #endif |
| 126 | +#endif |
| 127 | + |
115 | 128 | /** |
116 | 129 | * @} |
117 | 130 | */ |
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144 | 157 | const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \ |
145 | 158 | 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */ |
146 | 159 |
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147 | | -#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) |
| 160 | +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx) |
148 | 161 | const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \ |
149 | 162 | {2UL,6UL,4UL,3UL,2UL,4UL}, \ |
150 | 163 | {4UL,12UL,8UL,6UL,4UL,8UL}, \ |
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174 | 187 | */ |
175 | 188 | void SystemInit(void) |
176 | 189 | { |
| 190 | +#if defined(USER_VECT_TAB_ADDRESS) |
177 | 191 | /* Configure the Vector Table location add offset address ------------------*/ |
178 | | -#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS) |
179 | | - /* program in SRAMx */ |
180 | | - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAMx for CPU1 */ |
181 | | -#else /* program in FLASH */ |
182 | | - SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| 192 | + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; |
183 | 193 | #endif |
184 | 194 |
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185 | 195 | /* FPU settings ------------------------------------------------------------*/ |
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