@@ -122,21 +122,21 @@ static uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
122122
123123 RCC_OscInitStruct.PLL .PLLState = RCC_PLL_ON;
124124 RCC_OscInitStruct.PLL .PLLSource = RCC_PLLSOURCE_HSE;
125- RCC_OscInitStruct.PLL .PLLM = 8 ; // VCO input clock = 1 MHz (8 MHz / 8)
126- RCC_OscInitStruct.PLL .PLLN = 336 ; // VCO output clock = 336 MHz (1 MHz * 336 )
127- RCC_OscInitStruct.PLL .PLLP = RCC_PLLP_DIV4 ; // PLLCLK = 84 MHz (336 MHz / 4 )
128- RCC_OscInitStruct.PLL .PLLQ = 7 ; // USB clock = 48 MHz (336 MHz / 7 ) --> OK for USB
125+ RCC_OscInitStruct.PLL .PLLM = HSE_VALUE / 1000000L ; // Expects an 8 MHz external clock by default. Redefine HSE_VALUE if not
126+ RCC_OscInitStruct.PLL .PLLN = 192 ; // VCO output clock = 192 MHz (1 MHz * 192 )
127+ RCC_OscInitStruct.PLL .PLLP = RCC_PLLP_DIV2 ; // PLLCLK = 96 MHz (192 MHz / 2 )
128+ RCC_OscInitStruct.PLL .PLLQ = 4 ; // USB clock = 48 MHz (192 MHz / 4 ) --> OK for USB
129129 if (HAL_RCC_OscConfig (&RCC_OscInitStruct) != HAL_OK) {
130130 return 0 ; // FAIL
131131 }
132132
133133 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
134134 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
135- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
136- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
137- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
138- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
139- if (HAL_RCC_ClockConfig (&RCC_ClkInitStruct, FLASH_LATENCY_2 ) != HAL_OK) {
135+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
136+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
137+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
138+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
139+ if (HAL_RCC_ClockConfig (&RCC_ClkInitStruct, FLASH_LATENCY_3 ) != HAL_OK) {
140140 return 0 ; // FAIL
141141 }
142142
@@ -173,20 +173,20 @@ uint8_t SetSysClock_PLL_HSI(void)
173173 RCC_OscInitStruct.PLL .PLLState = RCC_PLL_ON;
174174 RCC_OscInitStruct.PLL .PLLSource = RCC_PLLSOURCE_HSI;
175175 RCC_OscInitStruct.PLL .PLLM = 16 ; // VCO input clock = 1 MHz (16 MHz / 16)
176- RCC_OscInitStruct.PLL .PLLN = 336 ; // VCO output clock = 336 MHz (1 MHz * 336 )
177- RCC_OscInitStruct.PLL .PLLP = RCC_PLLP_DIV4 ; // PLLCLK = 84 MHz (336 MHz / 4 )
178- RCC_OscInitStruct.PLL .PLLQ = 7 ; // USB clock = 48 MHz (336 MHz / 7 ) --> freq is ok but not precise enough
176+ RCC_OscInitStruct.PLL .PLLN = 192 ; // VCO output clock = 192 MHz (1 MHz * 192 )
177+ RCC_OscInitStruct.PLL .PLLP = RCC_PLLP_DIV2 ; // PLLCLK = 96 MHz (192 MHz / 2 )
178+ RCC_OscInitStruct.PLL .PLLQ = 4 ; // USB clock = 48 MHz (192 MHz / 4 ) --> freq is ok but not precise enough
179179 if (HAL_RCC_OscConfig (&RCC_OscInitStruct) != HAL_OK) {
180180 return 0 ; // FAIL
181181 }
182182
183183 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
184184 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
185- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
186- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
187- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
188- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
189- if (HAL_RCC_ClockConfig (&RCC_ClkInitStruct, FLASH_LATENCY_2 ) != HAL_OK) {
185+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
186+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
187+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
188+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
189+ if (HAL_RCC_ClockConfig (&RCC_ClkInitStruct, FLASH_LATENCY_3 ) != HAL_OK) {
190190 return 0 ; // FAIL
191191 }
192192
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