@@ -70,6 +70,9 @@ typedef enum {
7070#endif
7171#if defined(LPUART1_BASE )
7272 LPUART1_INDEX ,
73+ #endif
74+ #if defined(LPUART2_BASE )
75+ LPUART2_INDEX ,
7376#endif
7477 UART_NUM
7578} uart_index_t ;
@@ -210,6 +213,15 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
210213 obj -> irq = LPUART1_IRQn ;
211214 }
212215#endif
216+ #if defined(LPUART2_BASE )
217+ else if (obj -> uart == LPUART2 ) {
218+ __HAL_RCC_LPUART2_FORCE_RESET ();
219+ __HAL_RCC_LPUART2_RELEASE_RESET ();
220+ __HAL_RCC_LPUART2_CLK_ENABLE ();
221+ obj -> index = LPUART2_INDEX ;
222+ obj -> irq = LPUART2_IRQn ;
223+ }
224+ #endif
213225#if defined(UART7_BASE )
214226 else if (obj -> uart == UART7 ) {
215227 __HAL_RCC_UART7_FORCE_RESET ();
@@ -299,13 +311,17 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
299311 /* Set the NVIC priority for future interrupts */
300312 HAL_NVIC_SetPriority (obj -> irq , UART_IRQ_PRIO , UART_IRQ_SUBPRIO );
301313
302- #if defined(LPUART1_BASE )
314+ #if defined(LPUART1_BASE ) || defined( LPUART2_BASE )
303315 /*
304316 * Note that LPUART clock source must be in the range
305317 * [3 x baud rate, 4096 x baud rate]
306318 * check Reference Manual
307319 */
308- if (obj -> uart == LPUART1 ) {
320+ if ((obj -> uart == LPUART1 )
321+ #if defined(LPUART2_BASE )
322+ || (obj -> uart == LPUART2 )
323+ #endif
324+ ) {
309325 if (baudrate <= 9600 ) {
310326#if defined(USART_CR3_UCESM )
311327 HAL_UARTEx_EnableClockStopMode (huart );
@@ -326,24 +342,51 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
326342 if (baudrate <= 9600 ) {
327343 /* Enable the clock if not already set by user */
328344 enableClock (LSE_CLOCK );
329-
330- __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_LSE );
345+ if (obj -> uart == LPUART1 ) {
346+ __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_LSE );
347+ }
348+ #if defined(LPUART2_BASE )
349+ if (obj -> uart == LPUART2 ) {
350+ __HAL_RCC_LPUART2_CONFIG (RCC_LPUART2CLKSOURCE_LSE );
351+ }
352+ #endif
331353 if (HAL_UART_Init (huart ) == HAL_OK ) {
332354 return ;
333355 }
334356 }
335357 if (__HAL_RCC_GET_FLAG (RCC_FLAG_HSIRDY )) {
336- __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_HSI );
358+ if (obj -> uart == LPUART1 ) {
359+ __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_HSI );
360+ }
361+ #if defined(LPUART2_BASE )
362+ if (obj -> uart == LPUART2 ) {
363+ __HAL_RCC_LPUART2_CONFIG (RCC_LPUART2CLKSOURCE_HSI );
364+ }
365+ #endif
337366 if (HAL_UART_Init (huart ) == HAL_OK ) {
338367 return ;
339368 }
340369 }
341370#ifndef STM32H7xx
342- __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_PCLK1 );
371+ if (obj -> uart == LPUART1 ) {
372+ __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_PCLK1 );
373+ }
374+ #if defined(LPUART2_BASE )
375+ if (obj -> uart == LPUART2 ) {
376+ __HAL_RCC_LPUART2_CONFIG (RCC_LPUART2CLKSOURCE_PCLK1 );
377+ }
378+ #endif
343379 if (HAL_UART_Init (huart ) == HAL_OK ) {
344380 return ;
345381 }
346- __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_SYSCLK );
382+ if (obj -> uart == LPUART1 ) {
383+ __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_SYSCLK );
384+ }
385+ #if defined(LPUART2_BASE )
386+ if (obj -> uart == LPUART2 ) {
387+ __HAL_RCC_LPUART2_CONFIG (RCC_LPUART2CLKSOURCE_SYSCLK );
388+ }
389+ #endif
347390#else
348391 __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_CSI );
349392#endif
@@ -429,6 +472,13 @@ void uart_deinit(serial_t *obj)
429472 __HAL_RCC_LPUART1_CLK_DISABLE ();
430473 break ;
431474#endif
475+ #if defined(LPUART2_BASE )
476+ case LPUART2_INDEX :
477+ __HAL_RCC_LPUART2_FORCE_RESET ();
478+ __HAL_RCC_LPUART2_RELEASE_RESET ();
479+ __HAL_RCC_LPUART2_CLK_DISABLE ();
480+ break ;
481+ #endif
432482#if defined(UART7_BASE )
433483 case UART7_INDEX :
434484 __HAL_RCC_UART7_FORCE_RESET ();
@@ -544,6 +594,13 @@ void uart_config_lowpower(serial_t *obj)
544594 __HAL_RCC_LPUART1_CONFIG (RCC_LPUART1CLKSOURCE_HSI );
545595 }
546596 break ;
597+ #endif
598+ #if defined(LPUART2_BASE ) && defined(__HAL_RCC_LPUART2_CONFIG )
599+ case LPUART2_INDEX :
600+ if (__HAL_RCC_GET_LPUART2_SOURCE () != RCC_LPUART2CLKSOURCE_HSI ) {
601+ __HAL_RCC_LPUART2_CONFIG (RCC_LPUART2CLKSOURCE_HSI );
602+ }
603+ break ;
547604#endif
548605 }
549606 hsem_unlock (CFG_HW_RCC_CRRCR_CCIPR_SEMID );
@@ -866,7 +923,14 @@ void USART1_IRQHandler(void)
866923void USART2_IRQHandler (void )
867924{
868925 HAL_NVIC_ClearPendingIRQ (USART2_IRQn );
869- HAL_UART_IRQHandler (uart_handlers [UART2_INDEX ]);
926+ if (uart_handlers [UART2_INDEX ] != NULL ) {
927+ HAL_UART_IRQHandler (uart_handlers [UART2_INDEX ]);
928+ }
929+ #if defined(STM32G0xx ) && defined(LPUART2_BASE )
930+ if (uart_handlers [LPUART2_INDEX ] != NULL ) {
931+ HAL_UART_IRQHandler (uart_handlers [LPUART2_INDEX ]);
932+ }
933+ #endif
870934}
871935#endif
872936
@@ -907,7 +971,7 @@ void USART3_IRQHandler(void)
907971 if (uart_handlers [UART4_INDEX ] != NULL ) {
908972 HAL_UART_IRQHandler (uart_handlers [UART4_INDEX ]);
909973 }
910- #if defined(STM32F030xC )
974+ #if defined(STM32F030xC ) || defined( STM32G0xx ) && defined( LPUART2_BASE )
911975 if (uart_handlers [UART5_INDEX ] != NULL ) {
912976 HAL_UART_IRQHandler (uart_handlers [UART5_INDEX ]);
913977 }
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