@@ -548,6 +548,16 @@ extern "C" {
548548#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
549549#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
550550#endif /* STM32U5 */
551+ #if defined(STM32U0 )
552+ #define OB_USER_nRST_STOP OB_USER_NRST_STOP
553+ #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
554+ #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
555+ #define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
556+ #define OB_USER_nBOOT0 OB_USER_NBOOT0
557+ #define OB_USER_nBOOT1 OB_USER_NBOOT1
558+ #define OB_nBOOT0_RESET OB_NBOOT0_RESET
559+ #define OB_nBOOT0_SET OB_NBOOT0_SET
560+ #endif /* STM32U0 */
551561
552562/**
553563 * @}
@@ -1239,10 +1249,10 @@ extern "C" {
12391249#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12401250#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12411251
1242- #if defined(STM32H5 )
1252+ #if defined(STM32H5 ) || defined( STM32H7RS )
12431253#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12441254#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
1245- #endif /* STM32H5 */
1255+ #endif /* STM32H5 || STM32H7RS */
12461256
12471257#if defined(STM32WBA )
12481258#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1254,10 +1264,10 @@ extern "C" {
12541264#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12551265#endif /* STM32WBA */
12561266
1257- #if defined(STM32H5 ) || defined(STM32WBA )
1267+ #if defined(STM32H5 ) || defined(STM32WBA ) || defined( STM32H7RS )
12581268#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
12591269#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
1260- #endif /* STM32H5 || STM32WBA */
1270+ #endif /* STM32H5 || STM32WBA || STM32H7RS */
12611271
12621272#if defined(STM32F7 )
12631273#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1595,7 +1605,7 @@ extern "C" {
15951605#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
15961606#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
15971607
1598- #define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */
1608+ #define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
15991609
16001610/**
16011611 * @}
@@ -1807,7 +1817,7 @@ extern "C" {
18071817#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
18081818#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
18091819
1810- #define HAL_I2CFastModePlusConfig (SYSCFG_I2CFastModePlus , cmd ) ((cmd == ENABLE)? \
1820+ #define HAL_I2CFastModePlusConfig (SYSCFG_I2CFastModePlus , cmd ) ((( cmd) == ENABLE)? \
18111821 HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
18121822 HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
18131823
@@ -1989,12 +1999,12 @@ extern "C" {
19891999/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
19902000 * @{
19912001 */
1992- #if defined(STM32H5 ) || defined(STM32WBA )
2002+ #if defined(STM32H5 ) || defined(STM32WBA ) || defined( STM32H7RS )
19932003#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
19942004#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
19952005#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
19962006#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
1997- #endif /* STM32H5 || STM32WBA */
2007+ #endif /* STM32H5 || STM32WBA || STM32H7RS */
19982008
19992009/**
20002010 * @}
@@ -2309,8 +2319,8 @@ extern "C" {
23092319#define __HAL_COMP_EXTI_CLEAR_FLAG (__FLAG__ ) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
23102320 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
23112321 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
2312- # endif
2313- # if defined(STM32F302xE ) || defined(STM32F302xC )
2322+ #endif
2323+ #if defined(STM32F302xE ) || defined(STM32F302xC )
23142324#define __HAL_COMP_EXTI_RISING_IT_ENABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23152325 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23162326 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2343,8 +2353,8 @@ extern "C" {
23432353 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
23442354 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
23452355 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
2346- # endif
2347- # if defined(STM32F303xE ) || defined(STM32F398xx ) || defined(STM32F303xC ) || defined(STM32F358xx )
2356+ #endif
2357+ #if defined(STM32F303xE ) || defined(STM32F398xx ) || defined(STM32F303xC ) || defined(STM32F358xx )
23482358#define __HAL_COMP_EXTI_RISING_IT_ENABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23492359 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23502360 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2401,8 +2411,8 @@ extern "C" {
24012411 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
24022412 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
24032413 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
2404- # endif
2405- # if defined(STM32F373xC ) || defined(STM32F378xx )
2414+ #endif
2415+ #if defined(STM32F373xC ) || defined(STM32F378xx )
24062416#define __HAL_COMP_EXTI_RISING_IT_ENABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24072417 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
24082418#define __HAL_COMP_EXTI_RISING_IT_DISABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2419,7 +2429,7 @@ extern "C" {
24192429 __HAL_COMP_COMP2_EXTI_GET_FLAG())
24202430#define __HAL_COMP_EXTI_CLEAR_FLAG (__FLAG__ ) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
24212431 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
2422- # endif
2432+ #endif
24232433#else
24242434#define __HAL_COMP_EXTI_RISING_IT_ENABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24252435 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2721,6 +2731,12 @@ extern "C" {
27212731#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
27222732#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
27232733#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
2734+ #if defined(STM32C0 )
2735+ #define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
2736+ #define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
2737+ #define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
2738+ #define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
2739+ #endif /* STM32C0 */
27242740#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
27252741#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
27262742#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3644,8 +3660,12 @@ extern "C" {
36443660#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
36453661#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
36463662
3647- #if defined(STM32L4 ) || defined(STM32WB ) || defined(STM32G0 ) || defined(STM32G4 ) || defined(STM32L5 ) || \
3648- defined(STM32WL ) || defined(STM32C0 )
3663+ #if defined(STM32U0 )
3664+ #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
3665+ #endif
3666+
3667+ #if defined(STM32L4 ) || defined(STM32WB ) || defined(STM32G0 ) || defined(STM32G4 ) || defined(STM32L5 ) || \
3668+ defined(STM32WL ) || defined(STM32C0 ) || defined(STM32H7RS ) || defined(STM32U0 )
36493669#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36503670#else
36513671#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3747,8 +3767,10 @@ extern "C" {
37473767#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
37483768#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
37493769#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
3770+ #if !defined(STM32U0 )
37503771#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
37513772#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
3773+ #endif
37523774
37533775#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
37543776#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3894,7 +3916,7 @@ extern "C" {
38943916 */
38953917#if defined (STM32G0 ) || defined (STM32L5 ) || defined (STM32L412xx ) || defined (STM32L422xx ) || \
38963918 defined (STM32L4P5xx )|| defined (STM32L4Q5xx ) || defined (STM32G4 ) || defined (STM32WL ) || defined (STM32U5 ) || \
3897- defined (STM32WBA ) || defined (STM32H5 ) || defined (STM32C0 )
3919+ defined (STM32WBA ) || defined (STM32H5 ) || defined (STM32C0 ) || defined ( STM32H7RS ) || defined ( STM32U0 )
38983920#else
38993921#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39003922#endif
@@ -4217,6 +4239,9 @@ extern "C" {
42174239#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
42184240
42194241#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
4242+
4243+ #define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
4244+ #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
42204245/**
42214246 * @}
42224247 */
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