[STM32MP157_DK] System clock and HAL configuration

Author: kbumsik

system/STM32MP1xx/stm32mp1xx_hal_conf_default.h

@@ -19,7 +19,7 @@
   *
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32MP1xx_HAL_CONF_DEFAULT_H
@@ -37,6 +37,18 @@
   * @brief Include the default list of modules to be used in the HAL driver
   *        and manage module deactivation
   */
+
+#define HAL_RTC_MODULE_DISABLED /* RTC MODULE on Cortex-M side is not supported.
+                                   Linux on Cortex-A will handle this. */
+#define HAL_ETH_MODULE_DISABLED /* ETH module is also not intended to be used */
+#define HAL_MDMA_MODULE_ENABLED /* Some other modules (e.g. USART) require this */
+
+#if defined(ARDUINO_STM32MP157A_DK1) || defined(ARDUINO_STM32MP157A_DK2)
+// Cannot use them in this board, or define them in the kernel device tree.
+#define HAL_QSPI_MODULE_DISABLED
+#define HAL_FDCAN_MODULE_DISABLED
+#endif // defined(ARDUINO_STM32MP157A_DK1) && defined(ARDUINO_STM32MP157A_DK2)
+
 #include "stm32yyxx_hal_conf.h"
 #if 0
 /**

system/STM32MP1xx/system_stm32mp1xx.c

@@ -58,6 +58,10 @@
   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    4000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
 /**
   * @}
   */

variants/STM32MP157_DK/variant.cpp

@@ -128,14 +128,132 @@ extern "C" {
   * @param  None
   * @retval None
   */
-WEAK void SystemClock_Config(void)
+void SystemClock_Config(void)
 {
-  // Here copy the desired System Clock Configuration
-  // It could be generated thanks STM32CubeMX after code generation for Toolchain/IDE: 'SW4STM32',
-  // available in src/main.c
-  // or
-  // copied from a STM32CubeYY project examples
-  // where 'YY' could be F0, F1, F2, F3, F4, F7, G0, H7, L0, L1, L4, WB
+  /**
+   * NOTE: Because of the limitation of STM32MP1xx, unlike other MCUs this is
+   * NOT a WEAK function, preventing being overriden.
+   * In STM32MP1 series, SystemClock_Config()) is "done" by running the FSBL
+   * (First Stage Boot Loader) on Cortex-A. This function call shall NOT be
+   * executed in production mode. SystemClock_Config() shall be under 
+   * if(IS_ENGINEERING_BOOT_MODE()).
+   * 
+   * NOTE:
+   *  * Production mode: Both CA7 and CM4 core running, BOOT0 and BOOT2 are ON.
+   *  * Engineering mode: Only CM4 running, BOOT0 = OFF, BOOT2 = ON.
+   * See:
+   *  https://wiki.st.com/stm32mpu/wiki/STM32CubeMP1_development_guidelines
+   */
+  if(!IS_ENGINEERING_BOOT_MODE()) {
+    return;
+  }
+
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /**Configure LSE Drive Capability
+  */
+  HAL_PWR_EnableBkUpAccess();
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
+
+  /**Initializes the CPU, AHB and APB busses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
+                                      | RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = 16;
+  RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1;
+
+  /**PLL1 Config
+  */
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLL12SOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 3;
+  RCC_OscInitStruct.PLL.PLLN = 81;
+  RCC_OscInitStruct.PLL.PLLP = 1;
+  RCC_OscInitStruct.PLL.PLLQ = 1;
+  RCC_OscInitStruct.PLL.PLLR = 1;
+  RCC_OscInitStruct.PLL.PLLFRACV = 0x800;
+  RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL;
+  RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
+  RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
+
+  /**PLL2 Config
+  */
+  RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE;
+  RCC_OscInitStruct.PLL2.PLLM = 3;
+  RCC_OscInitStruct.PLL2.PLLN = 66;
+  RCC_OscInitStruct.PLL2.PLLP = 2;
+  RCC_OscInitStruct.PLL2.PLLQ = 1;
+  RCC_OscInitStruct.PLL2.PLLR = 1;
+  RCC_OscInitStruct.PLL2.PLLFRACV = 0x1400;
+  RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
+  RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
+  RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
+
+  /**PLL3 Config
+  */
+  RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE;
+  RCC_OscInitStruct.PLL3.PLLM = 2;
+  RCC_OscInitStruct.PLL3.PLLN = 34;
+  RCC_OscInitStruct.PLL3.PLLP = 2;
+  RCC_OscInitStruct.PLL3.PLLQ = 17;
+  RCC_OscInitStruct.PLL3.PLLR = 37;
+  RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1;
+  RCC_OscInitStruct.PLL3.PLLFRACV = 0x1A04;
+  RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
+  RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
+  RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
+
+  /**PLL4 Config
+  */
+  RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL4.PLLSource = RCC_PLL4SOURCE_HSE;
+  RCC_OscInitStruct.PLL4.PLLM = 4;
+  RCC_OscInitStruct.PLL4.PLLN = 99;
+  RCC_OscInitStruct.PLL4.PLLP = 6;
+  RCC_OscInitStruct.PLL4.PLLQ = 8;
+  RCC_OscInitStruct.PLL4.PLLR = 8;
+  RCC_OscInitStruct.PLL4.PLLRGE = RCC_PLL4IFRANGE_0;
+  RCC_OscInitStruct.PLL4.PLLFRACV = 0;
+  RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER;
+  RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
+  RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
+
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    /* Initialization Error */
+    while (1);
+  }
+  /**RCC Clock Config
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_ACLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+                                | RCC_CLOCKTYPE_PCLK3 | RCC_CLOCKTYPE_PCLK4
+                                | RCC_CLOCKTYPE_PCLK5 | RCC_CLOCKTYPE_MPU;
+  RCC_ClkInitStruct.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1;
+  RCC_ClkInitStruct.MPUInit.MPU_Div = RCC_MPU_DIV2;
+  RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2;
+  RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1;
+  RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3;
+  RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1;
+  RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2;
+  RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4;
+  RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
+    /* Initialization Error */
+    while (1);
+  }
+
+  /**Set the HSE division factor for RTC clock
+  */
+  __HAL_RCC_RTC_HSEDIV(24);
 }
 
 #ifdef __cplusplus