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Updated STM32L1xx CMSIS to v2.2.3
Included in STM32CubeL1 FW V1.8.1 Signed-off-by: Frederic.Pillon <frederic.pillon@st.com>
1 parent 4892d54 commit 2d70fc9

25 files changed

+1086
-332
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h‎

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -423,10 +423,12 @@ typedef struct
423423
typedef struct
424424
{
425425
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
426-
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
427-
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
426+
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
427+
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
428428
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
429-
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
429+
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
430+
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
431+
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
430432
} RI_TypeDef;
431433

432434
/**
@@ -5584,6 +5586,26 @@ typedef struct
55845586
#define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
55855587
#define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */
55865588

5589+
/******************** Bit definition for RI_HYSCR3 register ********************/
5590+
#define RI_HYSCR3_PE_Pos (0U)
5591+
#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
5592+
#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
5593+
#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
5594+
#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
5595+
#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
5596+
#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
5597+
#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
5598+
#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
5599+
#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
5600+
#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
5601+
#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
5602+
#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
5603+
#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
5604+
#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
5605+
#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
5606+
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
5607+
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
5608+
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
55875609

55885610
/******************************************************************************/
55895611
/* */

‎system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h‎

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -423,10 +423,12 @@ typedef struct
423423
typedef struct
424424
{
425425
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
426-
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
427-
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
426+
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
427+
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
428428
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
429-
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
429+
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
430+
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
431+
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
430432
} RI_TypeDef;
431433

432434
/**
@@ -5732,6 +5734,26 @@ typedef struct
57325734
#define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
57335735
#define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */
57345736

5737+
/******************** Bit definition for RI_HYSCR3 register ********************/
5738+
#define RI_HYSCR3_PE_Pos (0U)
5739+
#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
5740+
#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
5741+
#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
5742+
#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
5743+
#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
5744+
#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
5745+
#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
5746+
#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
5747+
#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
5748+
#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
5749+
#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
5750+
#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
5751+
#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
5752+
#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
5753+
#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
5754+
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
5755+
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
5756+
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
57355757

57365758
/******************************************************************************/
57375759
/* */

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