@@ -220,7 +220,7 @@ void SystemInit (void)
220220#endif
221221
222222#if defined (DATA_IN_D2_SRAM )
223- /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
223+ /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
224224#if defined(RCC_AHB2ENR_D2SRAM3EN )
225225 RCC -> AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN );
226226#elif defined(RCC_AHB2ENR_D2SRAM2EN )
@@ -333,27 +333,26 @@ void SystemCoreClockUpdate (void)
333333
334334 if (pllm != 0U )
335335 {
336- switch (pllsource )
337- {
336+ switch (pllsource )
337+ {
338338 case RCC_PLLCKSELR_PLLSRC_HSI : /* HSI used as PLL clock source */
339-
340- hsivalue = (HSI_VALUE >> ((RCC -> CR & RCC_CR_HSIDIV )>> 3 )) ;
341- pllvco = ( (float_t )hsivalue / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
342-
343- break ;
339+ hsivalue = (HSI_VALUE >> ((RCC -> CR & RCC_CR_HSIDIV )>> 3 )) ;
340+ pllvco = ( (float_t )hsivalue / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
341+ break ;
344342
345343 case RCC_PLLCKSELR_PLLSRC_CSI : /* CSI used as PLL clock source */
346344 pllvco = ((float_t )CSI_VALUE / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
347- break ;
345+ break ;
348346
349347 case RCC_PLLCKSELR_PLLSRC_HSE : /* HSE used as PLL clock source */
350348 pllvco = ((float_t )HSE_VALUE / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
351- break ;
349+ break ;
352350
353- default :
354- pllvco = ((float_t )CSI_VALUE / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
355- break ;
356- }
351+ default :
352+ hsivalue = (HSI_VALUE >> ((RCC -> CR & RCC_CR_HSIDIV )>> 3 )) ;
353+ pllvco = ((float_t )hsivalue / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
354+ break ;
355+ }
357356 pllp = (((RCC -> PLL1DIVR & RCC_PLL1DIVR_P1 ) >>9 ) + 1U ) ;
358357 common_system_clock = (uint32_t )(float_t )(pllvco /(float_t )pllp );
359358 }
@@ -364,7 +363,7 @@ void SystemCoreClockUpdate (void)
364363 break ;
365364
366365 default :
367- common_system_clock = CSI_VALUE ;
366+ common_system_clock = ( uint32_t ) ( HSI_VALUE >> (( RCC -> CR & RCC_CR_HSIDIV )>> 3 )) ;
368367 break ;
369368 }
370369
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